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TDC7200: Understanding Enable pin, Figure 18, Coarse Clock, Multi-Cycle Averaging

Part Number: TDC7200

Hi there,

I'm working on a custom PCB and and firmware to measure time between two laser pulses. IMHO, for some aspects the TDC7200 datasheet lacks clarity thus I'm raising my questions here to seek clarification. Thanks.

Enable Pin

The datasheet states: "it is essential that the ENABLE pin sees a positive edge after the device has powered up". In our design, the ENABLE pin is simply tied to VDD via a resistor. That seems to work.

Is that design ok or do I need a wait time between power up VDD and asserting ENABLE pin?

Figure 18

I agree with this posting that Figure 18 is misleading: I'd also extend the right hand side of "Clock_Countn" to the right hand side of "Timen+1" as that clearer indicates that CLOCK_COUNT counts full clock cycles and TIME counts fractional clock cycles. That is consistent with the formula for TOFn which substracts (Timen+1 * normLSB).

Does that make sense?

"Coarse Clock"

I wonder why the datasheet uses the term "coarse clock" for the cycles of the ring oscillator when obviously this counter has a rather fine resolution compared to the clock counter.

With that said, isn't coarse clock a misnomer and it should rather be "fine clock"?

Multi-Cycle Averaging

According to the datasheet, section 8.4.4. and specifically Figure 19, INTB is asserted only after all configured averaging cycles have been completed.

However, this posting states "Every time a measurement is completed INTB will pull low". I guess the datasheet is correct so this posting should rather read "After all configured averaging cycles are completed, INTB will be pulled low" (or something similar).

Further, the datasheet states that CLOCK_COUNTn registers need to be divided by the number of average cycles in order to calculate the mean value. In contrast to that TIMEn registers don't require this division. Obviously they already contain the mean value.

Is that understanding correct?

Thank you
Dan

  • Hi Dan,

    I am looking to these questions and will provide feedback by EOD today, 10/20.

  • Dan,

    Please see my feedback below.

    Enable Pin

    You do need to have a wait time between power up and asserting ENABLE.  I would suggest tying this to a GPIO similar to what we do in the EVM.  If you already have a PCB built which does not tie to a GPIO, you could possibly add some capacitance to the ENABLE pin to create some small delay for testing, but for production, I suggest using GPIO.

    Figure 18

    Yes, that does make sense.  I do think this figure could be updated to more accurately reflect the operation of the device. 

    "Coarse Clock"

    I was not in the group when the device was designed, but I see where you are coming from here.  Maybe it was named coarse counter since most of count information is coming from clock counter and a small amount from coarse counter.  Unfortunately, I don’t have the history on the decision.

    Multi-Cycle Averaging

    In the post regarding “every time a measurement is completed INTB will pull low”, this is referring to a measurement as a complete multi cycle averaged measurement. 

    Yes, that is correct.  The TIMEn registers are based on the internal oscillator and do not require division.

  • Dear ,

    Thank you for your helpful reply. I've now configured and tested the device and get correct and stable results.

    In a new design, I'll tie the "enable pin" to a GPIO.

    Regarding the term "Coarse Counter", I'd like vote for a change of this term. It's misleading in my opinion. The ring counter has a resolution of typ. 55 ps whereas the external oscillator provides a much "coarser" resolution in the 50 ns region

    In case there are updates to the TDC7200 datasheet, I'd also like to suggest to provide Figure 18 in a higher resolution. Currently, the text in the red/green/blue fields is unreadable to me:

    Thanks.
    Dan