IWR6843AOP: Custom PCB Boot Issues

Hi Yves,

1. Yes, it is correct that the voltages on the "1p4V_APLL" and 1p4V_SYNTH" pins will only come up only after RF_init API has been executed, Hence if you power up and check voltage it will still be zero. Hence, we need to check this voltage only when it's chirping. 

2. The QSPI Flash is programmed at 80MHz. The QSPI clock speed is increased to 80MHz from 40MHz to reduce the boot time for the flash loading.

3. It suggests that the device is not in correct SOP mode after 2nd NRESET release. We need to check every supply properly, if it's reaching the device. We should probe all the power supply from the source till the IWR6843AOP device and ensure that they are within the datasheet specifications. The nReset signal also needs to be checked. If SOP lines are set to the right state. Sometimes if the power supplies are out of spec limits or correct SOP modes are not latched during nReset the device may not boot up in correct SOP mode. 

Sometimes the device may boot up during initial power up due to overshoots. Please capture the SOP modes signal after 2nd NRESET release as well as the power supplies. The power supplies and SOP signals should be stable before the NRESET release for device to latch correct bootmode. 

Regards

Ankit

Thanks for the answers, we got to work and came with some measurements.

Measuring Power Supply

Power supply is within spec and all supplies are on, sequence is shown below.

Blue is 1.0v, Green is 1.2v, Purple is 1.8v, Yellow is 3.3v.

Measuring SOP’s

Yellow is nRESET, Purple is SOP0, Blue is SOP1, Green is SOP2

SOP measurement With 100n on nRESET, as in devkit but without gate (1^st nRESET):

Same setup, 2^nd nRESET:

Not much settling time so we tried a bit more capitance on the nRESET line, shown below.

SOP measurement with 200n on nRESET (1^st nRESET):

Same setup, 2^nd nRESET:

SOP’s seem to check out but nRESET signal comes on slow. Later we tried to use an STM32g031 to control the reset signal so we could have a controllable signal with less rise time. Results below:

Made no difference in behavior, same after 2^nd reset.

Measuring warmRESET

Yellow is nRESET, Purple is SOP0, Blue is warmRESET, Green is SOP2

As you can see the warmRESET is as expected, no faults here.

Measuring nERROR_OUT

Yellow is nRESET, Purple is SOP0, Blue is nERROR_OUT, Green is SOP2

SOP’s are configured to Flashing Mode:

As you can see in the above picture there are no errors in Flashing mode, but…

When the SOP’s are configured to Functional Mode:

In Functional mode “nERROR_OUT” shows an error, but not in Flashing mode.

Findings

NRST_PMIC is HIGH, so device is not in reset

I2C_SCL & I2C_SDA to PMIC are pulled high, but we do not see data.

Hello Yves,

Thanks for the oscilloscope captures. Also, NERROUT high during functional mode suggests some error in the hardware can we probe through the path of SOP switches to the device and check what is pulling it low during the 2nd reset.  Also please use 200n delay on the NRESET or STM32g031 to avoid incorrect boot mode latching as done in few captures.

Can you please share the schematic for the SOP settings.

Regards

Ankit

Hi Ankit,

Thanks for your response.

You can find the SOP schematics below:


Now that I look at it there is no active pulldown on SOP2, just tested it with a pulldown resistor, but no difference in behavior.

Yves,

The schematic seems to be correct. Some signal is pulling the SOP0 low after 2nd reset. Is JTAG connected to the device? Can you check if AR_TDO_SOP0 is pulling down the SOP signal. Or any other signals that could be connected to it (DCA, external host which may have internal pull down).

Regards

Ankit

Hi Ankit,

There is nothing else connected to "AR_TDO_SOP0", only what you see in the schematic above.
In all above measurements there is nothing connected to JTAG (no XDS110 and not even cables).

Kind regards,
Yves

Hi Yves,

Please share the complete schematic for review.

Regards

Ankit

Schematic Custom Board.pdf

Hello Ankit,

I have attached the schematic as *.pdf.

Kind regards,
Yves

Hi Yves,

Thank you sending the schematic; I have put it in the queue for schematic review and will respond by the end of next week with feedback. Please make sure the device is starting up by probing the XTAL capacitors(40MHz) and VBGAP (0.9V).

Meanwhile, could you please try connecting JTAG again and read the SOP registers.

SOP mode register: FFFF E268 (Flash mode should read 0x00000005, Functional Mode should read 0x00000001)

 Regards

Ankit

Hi Yves,

I checked that R172 and Q2 have been removed, how are you switching the SOP2 to 0 to be in functional mode. Also, please confirm if CLK_PMIC is DNP

Were you able to connect to JTAG and read the SOP mode register?

Regards

Ankit