We use our own FPGA acquisition board to receive the lvds data of iwr1443.
The lvds configuration turns on the HSI Header, and data transmission uses HW mode (SW mode is turned off), and datafmt is the ADC complex mode. There are 2 TXs working, number of loops, one chirp for each frame, number of loops is set to 2, so a total of 4 groups of lvds data are received, and the number of samples is 256. So far everything is correct.
One set of 1TX4RX data received a total of 2176 bytes of data, of which the first 64 bytes are hsiheader, and the check bit of hsiheader also corresponds correctly. But the remaining ADC part is 2112 bytes. When the number of samples is 256, 1TX4RX expects 256*2*2*4=4096 bytes were received, which cannot match the actual length of data received.
We were stuck on this issue for a long time and didn't know what was going on.
Hoping to get help.
Thanks!
