Other Parts Discussed in Thread: TMP461
Hi,
I have one question regarding the Data hold time t(HDDAT) in "Figure 1. Two-Wire Timing Diagram" in the Datasheet.
In my design (FPGA, acting as the IIC-Master), I set t(HDDAT) to 600 ns which is below t(HDDAT)max = 900ns and above t(HDDAT)min = 0ns.
That means, I will drive the SDA-line latest until a fixed time (clk-cycle driven) of 600 ns after the falling edge of SCL.
From my understanding, this would be Ok for the entire part of the Slave-ACK-Phase (when the master switches SDA from OUT -> IN) and when assuming 900 ns for "tHD;DAT".
-> after the falling edge of SCL, the master switches from OUT -> IN after 600ns, the Slave (TMP461) will do the switch from IN -> OUT (Slave drives ACK to the Master) 300ns later (in total 900ns)
-> Ok: Master and Slave both 'drive" SDA to IN (for a duration of 300 ns)
What would happen, when the Slave (TMP461) switches from IN -> OUT earlier than the 900 ns (because t(HDDAT) could be in the range between [0...900ns])?
-> let's assume the Slave switches from IN -> OUT after 300 ns after the falling edge of SCL
-> this would lead to a conflict (?):
-> after the falling edge of SCL, the master switches from OUT -> IN after 600ns, the Slave will do the switch from IN -> OUT 300ns earlier (!) (in total 300ns)
-> NOK (!?): Master 'drive" SDA to OUT and Slave also drive SDA to OUT (for a duration of 300 ns)
-> I think this is not really a problem, because OUT means for I2C not really OUT but a Tristate+Pull-up.
Is this assumption correct?
Do I have (the I2C-master) adapt the tHD;DAT time to avoid this bus-conflict on the SDA-line?
Thanks in advance for your answer!
Best Regards
Bodo Rauhut
