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Original question:

AWR2944: Enabling Instruction cache

AWR2944: AWR2944

Sheela Gajendran
Prodigy 80 points
Part Number: AWR2944

Hello,

Subject : Enable Cache 

1. In ARM Cortex-R Series Programmer Guide - version 1.0  , Link - "">developer.arm.com/.../System-Control-Register--SCTLR-"

          a) In System Control Register (SCTLR) - 

                 "I" bit - enables/disables Instruction cache

                 "C" bit - enables/disable data and unified caches

          b)  In MPU configuration -  MPU shall be enabled and the memory regions flags (for L1, MSS_L2 and DSS_L3 regions) can be defined as per the project needs.

2. This conflicts with another document -Cortex-R5 Technical reference Manual  r1p2,  Link - "">developer.arm.com/.../c1--System-Control-Register

        a) In System Control Register (SCTLR ) - 

                 "I" bit - Enables/disables L1 Instruction Cache

                 "C" bit - enables/disable  L1 data and unified caches

                 Here L1 memory is TCM memories and this around 128K. 

                 If these instructions only enables the TCM memory , then how to enable Cache for MSS_L2, DSS_L3 memories?

         b)  What is the impact of MPU configuration and defining the Memory region flags (for L1, MSS_L2 and DSS_L3 regions) in this case?

3. Can you please provide us the latest versions of the technical reference manuals and Programmers Guide for ArM cortex R5 to have consistent documents within our teams?

Regards,

Sheela

  • 0
    TI__Mastermind 22575 points

    Hi Sheela,

    Since AWR2944 uses the ARM Cortex-R5 core from ARM, we do not create any TRM or Programming guide for ARM core. You can refer to the ARM's website for the same.

    The difference in the wordings may be due the fact that the Programming guide is applicable to all Cortex-R series, whereas the ARM's TRM is specific to Cortex-R5.

    As in Cortex-R5, the Cache is implemented in the L1 region along with TCMA and TCMB memories. It is just a denotation that the physically the cache space is in L1. However, the Cache in AWR2944 can cache contents from any memory range (MSS_L2/DSS_L3) based on the config in ARM's core MPU.

    Regards,

    Ajay