Hello Ti Team ,
We are trying to enable INC for AWR2944 , based on your recommendations from our last meeting call , regarding the issue https://e2e.ti.com/e2eprivate/aptiv/aptiv-radar/f/aptiv-radar-srr7-forum/1322586/awr2944-pprotset2-register-is-not-getting-set .
As per your suggestion i have referred the ERRATA sheet i am trying to write to PPROTSET2 (0x2f78028) register and read them in 0x2f802c , to confirm whether the registers i specified are being written . I face two issues in this
1. Provide only supervisor write access to MSS_WDT
PROBLEM :
I Tried to enable supervisor write access for MSS_WDT and was trying to write a register RTIGCTRL in user mode .
I have configured MSS_CR5A_AHB_WR_ERR .
EXPECTATION :
we should have received MSS_CR5A_AHB_WR_ERR (interrupt 98 ) .when trying to access WDT register RTIGCTRL .
OBSERVATION:
1.We changed the value of RTIGCTRL to 0x03 . we are not receiving the interrupt .
2.As mentioned in ERRATA i am checking the 0x2f7802c to confirm if PPROTSET bit is set correctly.
2.Provide only supervisor write access to MSS_GIO
PROBLEM :
I Tried to enable supervisor write access to MSS_GIO and was trying to write a register GIODIRA in user mode .
I have configured MSS_CR5A_AHB_WR_ERR and have written PPROTSET2 (0x2f78028) by providing 0xffffffff (to confirm whether all bits are setting correctly) to write all bits and check if the bits are set .
EXPECTATION :
we should have received MSS_CR5A_AHB_WR_ERR (interrupt 98 ) .when trying to access GIODIRA
OBSERVATION:
1.I tried to write GIODIRA with 1 , we are not receiving the interrupt .
2.As mentioned in ERRATA i am checking the 0x2f7802c to confirm if PPROTSET bit is set correctly . The bits are not getting set properly .
