Hi,
My customer reported below issue related I2C slave operation.
SW: mmwave_sdk_03_05_00_04, libi2cSlave_xwr18xx.aer4f (I2C slave driver)
HW: ARM MCU board(I2C master), AWR1843BOOST(I2C Slave)
Issue description:
When data is written from slave to master using I2CSlave_write(), the function always returns "false".
But, at the master side, the data was properly received.
Then I2CSlave_write() is executed again, the function returns "true", while SDA, SCL signals stay at high level.
The same issue is reproduced with sample code (slave.c) as is.
Test conditions:
The I2C operation starts with "Start cond." => "Slave address (7bits) + Read(1bit)" => "Received data" => "Stop cond.".
("Restart cond." is not used.)
What the customer investigated:
They did some debug and found interrupts handling in I2CSlave_ISR function were done below order at Slave write.
#1: case I2C_IVR_INTCODE_XRDY (transmit)
#2: case I2C_IVR_INTCODE_AAS (slave address detect)
Because "ptrI2CMCB->transferInProgress = 1" is done at step#1, the program goes to "SemaphoreP_post(ptrI2CMCB->transferComplete)" path at step#2.
Then the program back to I2CSlave_setupTransfer(), an error happens as "ptrI2CMCB->mode != I2CSLAVE_IDLE_MODE".
FYI. in Slave read operation, interrupts are handled below order, so there is no issue.
#1: case I2C_IVR_INTCODE_AAS (slave address detect)
#2: case I2C_IVR_INTCODE_RRDY (receive)
Questions:
It seems the correct interrupts handling order should be below for Slave write operation.
#1: case I2C_IVR_INTCODE_AAS (slave address detect)
#2: case I2C_IVR_INTCODE_XRDY (transmit)
But I2C_IVR_INTCODE_XRDY comes first. Are there any reason?
BTW, the customer modified i2c_slave.c code as below and the issue is gone.
In I2CSlave_setupTransfer(), I2C_IVR_INTCODE_AAS is disabled (I2C_INT_MASK_ADRR_SLAVE) in Slave write operation.
Thanks and regards,
Koichiro Tashiro