AWR2944: Disable DSP L1D Cache in SBL

wu bin

Part Number: AWR2944

Hello, Expert

We want to disable DSP core L1D cache in SBL. Could you share the bit24(L1D_CACHE_MODE) of DSS_DSP_BOOTCFG Register detail descriptions?

Can we use DSS_DSP_BOOTCFG Register to disable DSP core L1D cache before DSP enters_c_int00()?

Wu Bin

9 months ago

0 Samhitha Bobba 9 months ago

TI__Genius 10660 points

Hi Wu Bin,

I need a day to check this. May I know the reason behind disabling L1D cache? Disabling cache will increase R/W time.

Regards,

Samhitha

0 wu bin 9 months ago in reply to Samhitha Bobba

Prodigy 110 points

We want to adjust L1D memory configuration to 011(16K for SRAM and 16K for cache). Now the defalut value of L1DMODE Setting in the L1DCFG Register is 111("Maximal Cache" Maps to 32K).

We meet the issue: Since we put .const to 16K SRAM from L1D memory, we found our const variable was modified in _c_int00().

Reason: L1D memory is default configuration as 32 D-Cache , But we modify L1DCFG Register in CacheP_init() in main(), so D-Cache can modify L1D memory of .const.

So we hope disable L1D cache in SBL, then change entry point of DSP to our function(such as _c_int000()), then we change L1D memory configuration to 011 in _c_int000(), then call _c_int00()

0 Samhitha Bobba 9 months ago in reply to wu bin

TI__Genius 10660 points

Hi Wu Bin,

wu bin said:
Reason: L1D memory is default configuration as 32 D-Cache , But we modify L1DCFG Register in CacheP_init() in main(), so D-Cache can modify L1D memory of .const.

Can you provide more details about when did you modify L1DCFG register?

Instead of modifying L1DCFG register in CacheP_init(), can you modify gCacheSize variable in mcu_plus_sdk_awr294x_09_00_00_15\source\kernel\.meta\dpl\cache_c6x.c.xdt.

CacheP_Size         gCacheSize = {
    .l1pSize = CacheP_L1Size_`instance.l1psize`K,
    .l1dSize = CacheP_L1Size_16K,
    .l2Size  = CacheP_L2Size_`instance.l2size`K,
};

Now rebuild your SBL and application and check L1DCFG register.

Regards,

Samhitha

0 wu bin 9 months ago in reply to Samhitha Bobba

Prodigy 110 points

Hello Samhitha,

We know we can modify gCacheSize to change L1D cache size oto 16K.

But it excutes in DSS core after main().

However the const value was loaded to L1D Cache before main(). and the values were modified in the function __init00() before main().

So we want to configure L1 D-cache size to 0(disable D-cache) in SBL.

We found DSS_DSP_BOOTCFG register can configure L1D_CACHE_MODE, but we don'r know how to use it? Could you share the detail descriptions of DSS_DSP_BOOTCFG register.

Regards,

Wu Bin

0 Samhitha Bobba 9 months ago in reply to wu bin

TI__Genius 10660 points

Hi Wu Bin,

I will check about DSS_DSP_BOOTCFG register description and let you know by Wednesday.

Regards,

Samhitha

+1 Samhitha Bobba 9 months ago in reply to Samhitha Bobba

TI__Genius 10660 points

Hi Wu Bin,

The DSS_DSP_BOOTCFG is used to configure L1P and L1D memories as cache or SRAM. Writing 1 to L1D_CACHE_MODE will configure L1D completely as SRAM. And Writing 0 to L1D_CACHE_MODE will configure L1D completely as Cache. Alternatively, you can also try adding assembly instructions to mcu_plus_sdk_awr294x_09_00_00_15\source\kernel\nortos\dpl\c66\HwiP_c66_asm.S in the following way before being branched out to c_int00. The following is a sample code. Rebuild nortos library and the application after modifying HwiP_c66_asm.S file.

Regards,

Samhitha

0 wu bin 9 months ago in reply to Samhitha Bobba

Prodigy 110 points

Thank you very much Samhitha.

0 wu bin 9 months ago in reply to Samhitha Bobba

Prodigy 110 points

Hi Samhitha,

We have modified the L1D_CACHE_MODE to set L1D as SRAM during SBL execution, but this modification is not work and the L1D cache is still 2-WAY Cache mode when DSP run.

The alternative solution is work, yet we are concerned about three constants (64, 3, and 0x01840000) modifying L1D memory(0xf00000 ~ 0xf04000).

Please whether the data from RAM to D-cache is initially loaded to the address 0x00f08000(from high address to low address)?

Regards,

Wu Bin

0 wu bin 9 months ago in reply to wu bin

Prodigy 110 points

Hello Samhitha,

The starting address is highest L1D memory, so it is a great solution for us to modify L1D cache mode in HwiP_c66_asm.S.

Regards,

Wu Bin

0 Samhitha Bobba 9 months ago in reply to wu bin

TI__Genius 10660 points

Hi Wu Bin,

I hope that your issue is resolved. I am closing this thread now.

Regards,

Samhitha

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AWR2944: Disable DSP L1D Cache in SBL