Hello Team,
I am implementing dual clock comparator safety module and there is a need to compare DSS clocks in DSS DCC-A and DSS DCC-B instances. I had done MSS clock monitoring for few pairs of clocks in 4 MSS instances (MSS DCCA, DCCB, DCCC and DCCD). But for DSS clock monitoring I am facing some issues in the DCC counter register values like the clock frequencies are not stable and seems fluctuating. When I went through the Technical Reference Manual, in the Device block Diagram, it shows DCC#4 in MSS core and DCC#2 in DSS core. So can you please confirm whether the DSS clock monitoring can be done in MSS core also or this monitoring has to be written in DSS core itself?
As per the descriptions in the document, what I understood is that the DCC#2 are the 2 DCC instances in DSS core (DSS DCCA and DSS DCCB) and DCC#4 means MSS DCCA, MSS DCCB, MSS DCCC and MSS DCCD in MSS core.