AWR1843: AWR1843 Fall time of I2C SCL timing

Ken Zhang

Part Number: AWR1843

Hi Experts

1.In AWR1843 DS, the fall time of I2C interface is not provided, Could you pls tell the min and max range of SCL fall time （t f(SCL)）？

2. Customer also find that Pulse duration of SCL low ( t w(SCLL) ) measured on their board is 1.25us which is slightly less than 1.3 us in DS, will it cause any problems?

Thanks

Ken

8 months ago

+1 Josh Wyatt 8 months ago

TI__Guru* 91206 points

Dear Ken -

Thanks for the post and the observation. Here I think the note below the diagram implies that this device should comply with the I2C spec

With regards to tlow - this would only possibly cause an issue if using a higher clock frequency.

0 Ken Zhang 8 months ago in reply to Josh Wyatt

TI__Intellectual 2865 points

Hi Josh

Thanks for reaching out to help!

Which document does the snapshot come from? Is there any solution that helps enlarge tlow of I2C timing?

Thanks

Ken

0 Josh Wyatt 8 months ago in reply to Ken Zhang

TI__Guru* 91206 points

Ken -

The screenshot is from I2C spec. What SCL frequency are you operating at?

0 Ken Zhang 8 months ago in reply to Josh Wyatt

TI__Intellectual 2865 points

Hi Josh

It works under 400KHz.

+1 Josh Wyatt 8 months ago in reply to Ken Zhang

TI__Guru* 91206 points

Ken - OK, so it should never be an issue then - also just FYI, i have seen this measurement done incorrectly plenty of times - if it comes up again as an experienced issue, if checking - make sure they follow the 70%VDD/30%VDD method shown in I2C diagrams for VIL and VIH. from I2C spec, and based on speed/frequency of SCL.

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AWR1843: AWR1843 Fall time of I2C SCL timing