We have designed the SPI transmission something like this.
As per this design, we expect the data of read buffer to come in next write job. However, the data received is inconsistent. Sometimes, we receive the read request data in the same read receive buffer while some other time, we receive the data in write receive buffer.
In the below example:
We are reading from testconfig register and writing to test config register in the same cycle (async transmit with 2 jobs, read first followed by a write)
First values obtained:
After a cpu reset, we obtain values like this
Could you please suggest what is going wrong in this situation?