AWR1843AOPEVM: Layer1 pattern of EVM PCB

Shoko Sakaguchi

Intellectual 450 points

Part Number: AWR1843AOPEVM
Other Parts Discussed in Thread: AWR1843AOP

Hello,

I have a question about AWR1843AOPEVM PCB.

Regarding Layer1 pattern of EVM PCB, please let me know why the GND pattern is removed around AWR1843AOP.

Plese advise.

Best regards,

Shoko

8 months ago

0 James Murdock65 8 months ago

TI__Expert 3171 points

Hello Shoko-san,

There should still be ground - e.g. see below:

0 Shoko Sakaguchi 8 months ago in reply to James Murdock65

Intellectual 450 points

Hello James,

I have alredy know there is GND pattern on Layer2.

I want to know why there is not GND pattern around AWR1843AOP on LAYER1.

If you don't know about it, could you please change to someone who can be expert on PCB pattern?

Please advise.

Best regards,

Shoko

0 James Murdock65 8 months ago in reply to Shoko Sakaguchi

TI__Expert 3171 points

Hello Shoko-san,

I'm following up with my team about this. However, may I ask why you want to know about this? Here are my thoughts:

1. for antenna performance, the ground in the next layer down is sufficient for ground, and the design was simulated thusly. Additionally, since this is AOP its important to not have any 'incorrect' structures too close to the antenna that could impact the antenna's performance/pattern/matching etc.

Regards,

James

+1 James Murdock65 8 months ago in reply to James Murdock65

TI__Expert 3171 points

Hello Shoko-san,

After checking with my team, I understand that this was done to eliminate surface wave effects near the antenna. Generally speaking, we do suggest there to be no PCB above and below the device (even though this is not 100% followed in the reference design, that is the general recommendation).

AWR1843AOP Device Errata, Silicon Revision 1.0 (Rev. A) (ti.com)

Regards,

James

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AWR1843AOPEVM: Layer1 pattern of EVM PCB