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AWR1843BOOST: Query on the parameters of DCA1000EVM: raw ADC data capture and data processing

Mohan C
Prodigy 130 points
Part Number: AWR1843BOOST
Other Parts Discussed in Thread: AWR1843

Hi,

I'm trying to capture 1 frame raw ADC data from AWR1843 via DCA1000 EVM through a custom PC server application.

Below were the radar configuration: ("profile_2d" configuration file taken as reference configuration file)

sensorStop
flushCfg
dfeDataOutputMode 1
channelCfg 15 5 0
adcCfg 2 1
adcbufCfg -1 0 1 1 1
lowPower 0 0
profileCfg 0 77 7 3 39 0 0 100 1 256 7200 0 0 30
chirpCfg 0 0 0 0 0 0 0 1
chirpCfg 1 1 0 0 0 0 0 4
frameCfg 0 1 32 1 100 1 0
guiMonitor -1 1 1 1 0 0 1
cfarCfg -1 0 2 8 4 3 0 15.0 0
cfarCfg -1 1 0 4 2 3 1 15.0 0
multiObjBeamForming -1 1 0.5
calibDcRangeSig -1 0 -5 8 256
clutterRemoval -1 0
compRangeBiasAndRxChanPhase 0.0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
measureRangeBiasAndRxChanPhase 0 1. 0.2
aoaFovCfg -1 -90 90 -90 90
cfarFovCfg -1 0 0.25 8.64
cfarFovCfg -1 1 -10.59 10.59
extendedMaxVelocity -1 0
CQRxSatMonitor 0 3 11 121 0
CQSigImgMonitor 0 127 8
analogMonitor 0 0
lvdsStreamCfg -1 1 1 1
calibData 0 0 0
sensorStart

Below were the FGPA configuration for raw ADC data capture / Record:

configFpga_Req.header = UDP_HEADER;                                       //0xA55A
configFpga_Req.command = FPGA_CONFIG_CMD;                       //0x03
configFpga_Req.size = 6;
configFpga_Req.dataLogMode = RAW_MODE_LOGGING;             //1
configFpga_Req.lvdsMode = LANE2_LVDS_MODE;                        //2
configFpga_Req.dataTransferMode = LVDS_CAPTURE_MODE;    //1
configFpga_Req.dataCaptureMode = ETHERNET_STREAM;         //2
configFpga_Req.dataFormatMode = DATA_FMT_16;                      //3
configFpga_Req.timer = 30;
configFpga_Req.footer = UDP_FOOTER;                                        //0xEEAA

1. Can you verify the radar configuration parameters to transmit raw ADC data over LVDS mode.

2. What is the size of 1 frame raw ADC data?  

since "channelCfg 15 5 0" is configured to enable all 4Rx channels. The "lvdsMode" is set to LANE2_LVDS_MODE. Does raw ADC data contains all Rx0, Rx1, Rx2, Rx3 data or contains only Rx0, Rx1 data?

How to calculate the frame size?

3. Can you explain the frame format of DCA1000 UDP packet of raw ADC data. Information related to RX real and imaginary data sequence?

4. In radar configuration "lvdsStreamCfg -1 1 1 1", SW HSI header is enabled. Is header will be added to every frame or not?

How to distinguish the each frame from the raw ADC data?

  • +1
    TI__Expert 4480 points

    1. Yes, you can verify that by checking the size of .bin file that is generated.

    2. the formula for calculation is Size of ADC data = no of Frames * no of ChirpLoops * no of Chirps * no of Rx * no of ADCSamples * Sampling_type * bytes_per_sample. It contains data of all Rx. For Real sampling type put 1 and for complex sampling type put 2 and bytes per sample is 2.

    3.

    4. Yes, it will be added to each header.