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AWR2944: AWR2944 ES1.0 to ES2.0 the CSi2 mode cannot receive

shi guilin
Prodigy 181 points
Part Number: AWR2944
Other Parts Discussed in Thread: SYSCONFIG, UNIFLASH

Hi,

    I debugged the CSI2 mode by running it on the AWR 2844 ES1.0.

    but when zhe AWR2944 ES1.0 to ES2.0 changes,zhe CSI2 mode cannot receive.

    There are no changes related to CSI2 in the modification information from ES1.0 to ES2.0.

   May I ask if there is any good solution?

Regards,

guilin.shi

  • 0 in reply to Saswat Kumar
    Prodigy 181 points

    Hello Saswat,

      My ES 1.0 configure PLL function using SDK mmwave_sdk_03_01_01_02.Here are the configuration functions

    ======

    void Bootloader_socConfigurePll(void)
    {
        SOC_RcmPllHsDivOutConfig hsDivCfg;
        SOC_RcmEfuseBootFreqConfig bootFreqEfuseCfg;
        int32_t retVal;
        uint32_t defaultR5Clk;

        retVal = SOC_rcmSetHSDivMux(SOC_RcmHSDIVClkOutMuxId_DPLL_CORE_OUT2,
                                    SOC_RcmHSDIVClkOutMuxClockSource_DPLL_CORE_HSDIV0_CLKOUT2_PreMux);
        DebugP_assert(retVal == SystemP_SUCCESS);

        hsDivCfg.hsdivOutEnMask = (SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_1 |
                                    SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_2);
        /* Configure CLKOUT1 to DSS PLL Fout/2. Divider is hsDivOut + 1 so set 1 */
        hsDivCfg.hsDivOutFreqHz[1] = SOC_RCM_FREQ_MHZ2HZ(360U);
        hsDivCfg.hsDivOutFreqHz[2] = SOC_RCM_FREQ_MHZ2HZ(240U);
        SOC_rcmDspPllConfig(SOC_RcmPllFoutFreqId_CLK_720MHZ, &hsDivCfg);
        retVal = SOC_rcmSetHSDivMux(SOC_RcmHSDIVClkOutMuxId_DPLL_DSP_OUT1,
                            SOC_RcmHSDIVClkOutMuxClockSource_DPLL_DSP_HSDIV0_CLKOUT1_PreMux);
        DebugP_assert(retVal == SystemP_SUCCESS);
        retVal = SOC_rcmSetHSDivMux(SOC_RcmHSDIVClkOutMuxId_DPLL_DSP_OUT2,
                            SOC_RcmHSDIVClkOutMuxClockSource_DPLL_DSP_HSDIV0_CLKOUT2_PreMux);
        DebugP_assert(retVal == SystemP_SUCCESS);

        hsDivCfg.hsdivOutEnMask = SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_1;
        /* Configure CLKOUT1 to DSS PLL Fout/2. Divider is hsDivOut + 1 so set 1 */
        hsDivCfg.hsDivOutFreqHz[1] = SOC_RCM_FREQ_MHZ2HZ(200U);
        SOC_rcmPerPllConfig(SOC_RcmPllFoutFreqId_CLK_1800MHZ, &hsDivCfg);
        retVal = SOC_rcmSetHSDivMux(SOC_RcmHSDIVClkOutMuxId_DPLL_PER_OUT1,
                            SOC_RcmHSDIVClkOutMuxClockSource_DPLL_PER_HSDIV0_CLKOUT1_PreMux);
        DebugP_assert(retVal == SystemP_SUCCESS);

        SOC_rcmGetEfuseBootFrequency(&bootFreqEfuseCfg);

        SOC_rcmSetR5Clock(bootFreqEfuseCfg.r5FreqHz, bootFreqEfuseCfg.sysClkFreqHz);

        SOC_rcmSetRssClkFreq(SOC_RcmRssClkSrcId_DPLL_PER_HSDIV0_CLKOUT1_MUXED, SOC_RCM_FREQ_MHZ2HZ(200U));

        /* For AWR change the UART clock to PER HSDIV CLKOUT1 insted of SYSCLK.
         * R5 clock and Sysclk is updated during boot up */
        SOC_rcmSetPeripheralClock(SOC_RcmPeripheralId_MSS_SCIA,
                                  SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT1,
                                  SOC_RCM_FREQ_MHZ2HZ(200U));

        hsDivCfg.hsdivOutEnMask = (SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_0 |
                                    SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_2 |
                                    SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_3);
        /* RCM_PLL_HSDIV_OUTPUT_IDX0 to boot frequency R5 clock. */
        hsDivCfg.hsDivOutFreqHz[0] = bootFreqEfuseCfg.r5FreqHz;
        hsDivCfg.hsDivOutFreqHz[2] = SOC_RCM_FREQ_MHZ2HZ(240U);
        hsDivCfg.hsDivOutFreqHz[3] = SOC_RCM_FREQ_MHZ2HZ(200U);
        SOC_rcmApllHSDivConfig(SOC_RcmAPLLID_1P2G, &hsDivCfg);

        /* Change the CORE clock source to APLL 1P2G HSDIV0 CLKOUT0. */
        retVal = SOC_rcmSetHSDivMux(SOC_RcmHSDIVClkOutMuxId_DPLL_CORE_OUT2,
                            SOC_RcmHSDIVClkOutMuxClockSource_APLL_1p2G_HSDIV0_CLKOUT0);
        DebugP_assert(retVal == SystemP_SUCCESS);

        /* CORE ADPLL reconfiguration. */
        hsDivCfg.hsdivOutEnMask = (SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_1 |
                                   SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_2);
        hsDivCfg.hsDivOutFreqHz[1] = SOC_RCM_FREQ_MHZ2HZ(500U);
        hsDivCfg.hsDivOutFreqHz[2] = gCoreBootInfo[CSL_CORE_ID_R5FSS0_0].defaultClockHz;

        SOC_rcmCoreDpllConfig(SOC_RcmPllFoutFreqId_CLK_1500MHZ, &hsDivCfg);

        /* Change the CORE clock source back to DPLL CORE HSDIV0 CLKOUT2. */
        retVal = SOC_rcmSetHSDivMux(SOC_RcmHSDIVClkOutMuxId_DPLL_CORE_OUT2,
                                    SOC_RcmHSDIVClkOutMuxClockSource_DPLL_CORE_HSDIV0_CLKOUT2_PreMux);
        DebugP_assert(retVal == SystemP_SUCCESS);

        defaultR5Clk = gCoreBootInfo[CSL_CORE_ID_R5FSS0_0].defaultClockHz;
        SOC_rcmSetR5Clock(defaultR5Clk, defaultR5Clk/2);
    }

    ======

    I am actually more concerned about why my settings for the gate_ctrl register did not take effect. I don't know if it's a problem with my setup method.

    Regards,

    guilin.shi

  • 0 in reply to shi guilin
    TI__Mastermind 35295 points

    Hello Shi guilin,

    In the latest SDK can you remove the following line of code:

        /* APLL 1.2 */
        SOC_rcmApllHSDivDisableOutput(SOC_RcmAPLLID_1P2G, SOC_RCM_PLL_HSDIV_OUTPUT_IDX0);
        SOC_rcmApllHSDivDisableOutput(SOC_RcmAPLLID_1P2G, SOC_RCM_PLL_HSDIV_OUTPUT_IDX1);
        SOC_rcmApllHSDivDisableOutput(SOC_RcmAPLLID_1P2G, SOC_RCM_PLL_HSDIV_OUTPUT_IDX2);

        /* APLL 1.8 */
        SOC_rcmApllHSDivDisableOutput(SOC_RcmAPLLID_1P8G, SOC_RCM_PLL_HSDIV_OUTPUT_IDX0);
        SOC_rcmApllHSDivDisableOutput(SOC_RcmAPLLID_1P8G, SOC_RCM_PLL_HSDIV_OUTPUT_IDX1);
        SOC_rcmApllHSDivDisableOutput(SOC_RcmAPLLID_1P8G, SOC_RCM_PLL_HSDIV_OUTPUT_IDX2);
        SOC_rcmApllHSDivDisableOutput(SOC_RcmAPLLID_1P8G, SOC_RCM_PLL_HSDIV_OUTPUT_IDX3);

        /* COREDPLL CLOCKOUT0 */
        SOC_rcmDpllHSDivDisableOutput(SOC_RCM_DPLL_CORE, SOC_RCM_PLL_HSDIV_OUTPUT_IDX0);

        /* PER PLL */
        SOC_rcmDpllHSDivDisableOutput(SOC_RCM_DPLL_PER, SOC_RCM_PLL_HSDIV_OUTPUT_IDX0);
        SOC_rcmDpllHSDivDisableOutput(SOC_RCM_DPLL_PER, SOC_RCM_PLL_HSDIV_OUTPUT_IDX2);
        SOC_rcmDpllHSDivDisableOutput(SOC_RCM_DPLL_PER, SOC_RCM_PLL_HSDIV_OUTPUT_IDX3);

        /* DSP PLL */
        SOC_rcmDpllHSDivDisableOutput(SOC_RCM_DPLL_DSS, SOC_RCM_PLL_HSDIV_OUTPUT_IDX0);
        SOC_rcmDpllHSDivDisableOutput(SOC_RCM_DPLL_DSS, SOC_RCM_PLL_HSDIV_OUTPUT_IDX3);
    In the function Bootloader_socConfigurePllPostApllSwitch and then try out? 

    Regards,
    Saswat Kumar




  • 0 in reply to Saswat Kumar
    Prodigy 181 points

    Hello Saswat,

       The above code modification is valid for the gate_ctrl setting, but only successfully configuring the PLL_PER_HSDIVIDER-CLKOUT2 register does not allow the CSI2 module to receive it properly.
      Excuse me, do you know what clock and frequency CSI2 uses when configuring ES1.0?

    Regards,

    guilin.shi

  • 0 in reply to shi guilin
    TI__Mastermind 35295 points

    Hello Shi guillin,

    I am not aware of the default value, whenever I use I always ensure to set the values of this myself in the application as that is a better practice of coding any device.
    On your Es 1.0 based on the clk_src_sel value you can tell which is the clock source, in your case If I remember was 0x0  itself, so based on the clock source you can find out.

    shi guilin said:
    The above code modification is valid for the gate_ctrl setting, but only successfully configuring the PLL_PER_HSDIVIDER-CLKOUT2 register does not allow the CSI2 module to receive it properly

    What do you mean by this? We need to ungate your clocks right?, the previous debugs I can see that your clock was not successfully gated. What is not receiving properly?

    Regards,
    Saswat Kumar

  • 0 in reply to shi guilin
    Prodigy 181 points

    Hello Shi guilin,
       My clock can successfully gated,but CSI2 can't reset done to receiving.

      I configure the clock to ensure that the CSI2 module works properly
      I will try different clock settings and share any new developments with you. If you have any ideas about setting up the CSI2 module for ES2.0, you can also share them with me.

    Regards,
    Saswat Kumar

  • 0 in reply to shi guilin
    Prodigy 181 points

    Hello Saswat,

       My clock can successfully gated,but CSI2 can't reset done to receiving.

      I configure the clock to ensure that the CSI2 module works properly
      I will try different clock settings and share any new developments with you. If you have any ideas about setting up the CSI2 module for ES2.0, you can also share them with me.

    Sorry, the title in the previous message was written incorrectly!!!

    Regards,

    guilin.shi

  • 0 in reply to shi guilin
    TI__Mastermind 35295 points

    Hello Shi guilin,

    Don't gate the clock, the point is to ungate it. Gating the clocks will stop the clock supply.

    Regards,
    Saswat Kumar

  • 0 in reply to Saswat Kumar
    Prodigy 181 points

    Hello Saswat,

      What is the clock and frequency used by CSI2 if CSIRX-CLK-SRC-SEL and CSIRX-DIV_VAL are configured to 0?
      In the ES1.0 program, it is configured as 0.

    I have now configured PLL_PER_HSDIVIDER-CLKOUT 0~3, CSIRX-CLK-SRC-SEL, and CSIRX-DIV_VAL to be consistent with ES1.0, but the CSI2 module still cannot be initialized.

      Do you have any suggestions?

    Regards,

    guilin.shi

  • 0 in reply to shi guilin
    TI__Mastermind 35295 points

    Hello Shi guilin,

    In the ES 1.0 can you try to set another clock source instead of default?
    It shows reserved if you see:

    When I checked with my team also they told that it should never be used in default as that has not been validated.
    Can you try ES 1.0 with a proper clock source and see if it works?

    Regards,
    Saswat Kumar

  • 0 in reply to Saswat Kumar
    Prodigy 181 points

    Hello Saswat,

    I tried to configure CSIRX-CLK-SRC-SEL and CSIRX-DIV_VAL in ES1.0, and configuring 0 resulted in the same effect as 1.

    However, the CSI2 module of the ES2.0 chip with the same configuration still cannot function properly.
    I am using the same program. (Because sdk mmwave_mcuplus_sdk_04:04_1-02 can run on chips of ES1.0 and ES2.0)

    Regards,

    guilin.shi

  • 0 in reply to shi guilin
    TI__Mastermind 35295 points

    Hello Shi guilin,

    What I meant was in ES 1.0 use a proper source as per the table and not configure it to 0 as it is a reserved source.

    Regards,
    Saswat Kumar

  • 0 in reply to Saswat Kumar
    Prodigy 181 points

    Hello Saswat,

    What I mean is that on ES1.0, I set both the CSIRX-CLK-SRC-SEL and CSIRX-DIV_VAL registers to 1. The CSI2 module can function properly.
    The final effect of CSI2 is consistent with setting it to 0.

    =====

        unsigned int* p1;
        p1 = (unsigned int*)0x02140018u;
        *p1 = 0x111u;
        p1 = (unsigned int*)0x02140044u;
        *p1 = 0x111u;

    =====

    Regards,

    guilin.shi

  • 0 in reply to shi guilin
    TI__Mastermind 35295 points

    Hello Shi guilin,

    Can you please help me understand this, I am unable to understand.

    shi guilin said:
    The final effect of CSI2 is consistent with setting it to

    I only understood that you are setting that register.
    I didnt understand the second line.

    Regards,
    Saswat Kumar

  • 0 in reply to Saswat Kumar
    Prodigy 181 points

    Hello Saswat,

    When we first communicated this issue, the CSI2 module was working properly on ES1.0. We read that the values of the CSIRX-CLK-SRC-SEL and CSIRX-DIV_VAL registers are both 0
    When I set the values of the CSIRX-CLK-SRC-SEL and CSIRX-DIV_VAL registers to 1, the CSI2 module can also function properly on ES1.0.
    I understand these two settings, and the clock frequency setting of CSI2 is consistent.

    Regards,

    guilin.shi

  • 0 in reply to shi guilin
    Prodigy 181 points

    Hello Saswat,

    I ran the same program on both ES1.0 and ES2.0 chips. Here is the MSS_TOPRCM register information for my dump, please help check it.

    Fullscreen MSS_TOPRCM_ES1.0.txt Download 
    [0 ... 99]			
	PID	0x61800214	PID register  [Memory Mapped]	
	HW_REG0	0x00000000	Memory Mapped	
	HW_REG1	0x00000000	Memory Mapped	
	PREVIOUS_NAME	0x00000000	Memory Mapped	
	HW_REG3	0x00000000	Memory Mapped	
	HSI_CLK_SRC_SEL	0x00000333	Memory Mapped	
	CSIRX_CLK_SRC_SEL	0x00000222	Memory Mapped	
	MCUCLKOUT_CLK_SRC_SEL	0x00000000	Memory Mapped	
	PMICCLKOUT_CLK_SRC_SEL	0x00000000	Memory Mapped	
	OBSCLKOUT_CLK_SRC_SEL	0x00000000	Memory Mapped	
	TRCCLKOUT_CLK_SRC_SEL	0x00000000	Memory Mapped	
	CSIRX_DIV_VAL	0x00000111	Memory Mapped	
	MCUCLKOUT_DIV_VAL	0x00000000	Memory Mapped	
	PMICCLKOUT_DIV_VAL	0x00000000	Memory Mapped	
	OBSCLKOUT_DIV_VAL	0x00000000	Memory Mapped	
	TRCCLKOUT_DIV_VAL	0x00000000	Memory Mapped	
	CSIRX_CLK_GATE	0x00000000	Memory Mapped	
	MCUCLKOUT_CLK_GATE	0x00000007	Memory Mapped	
	PMICCLKOUT_CLK_GATE	0x00000007	Memory Mapped	
	OBSCLKOUT_CLK_GATE	0x00000000	Memory Mapped	
	TRCCLKOUT_CLK_GATE	0x00000000	Memory Mapped	
	DSS_CLK_GATE	0x00000000	Memory Mapped	
	HSI_CLK_STATUS	0x00000004	Memory Mapped	
	CSIRX_CLK_STATUS	0x00000104	Memory Mapped	
	MCUCLKOUT_CLK_STATUS	0x00000100	Memory Mapped	
	PMICCLKOUT_CLK_STATUS	0x00000100	Memory Mapped	
	OBSCLKOUT_CLK_STATUS	0x00000001	Memory Mapped	
	TRCCLKOUT_CLK_STATUS	0x00000001	Memory Mapped	
	WARM_RESET_CONFIG	0x00070707	Memory Mapped	
	SYS_RST_CAUSE	0x00000009	Memory Mapped	
	SYS_RST_CAUSE_CLR	0x00000000	Memory Mapped	
	DSS_RST_CTRL	0x00000000	Memory Mapped	
	RS232_BITINTERVAL	0x6C815D5B	Memory Mapped	
	LVDS_PAD_CTRL0	0x00000000	Memory Mapped	
	LVDS_PAD_CTRL1	0x02000000	Memory Mapped	
	DFT_DMLED_EXEC	0x00000000	Memory Mapped	
	DFT_DMLED_STATUS	0x00000000	Memory Mapped	
	LIMP_MODE_EN	0x00000000	Memory Mapped	
	PMICCLKOUT_DCDC_CTRL	0x00000000	Memory Mapped	
	PMICCLKOUT_DCDC_SLOPE	0x00000000	Memory Mapped	
	RCOSC32K_CTRL	0x00000000	Memory Mapped	
	ANA_HSI2DIGCLK_GATE	0x00000007	Memory Mapped	
	PLL_CORE_PWRCTRL	0x00000030	Memory Mapped	
	PLL_CORE_CLKCTRL	0x28134801	Memory Mapped	
	PLL_CORE_TENABLE	0x00000000	Memory Mapped	
	PLL_CORE_TENABLEDIV	0x00000000	Memory Mapped	
	PLL_CORE_M2NDIV	0x00010013	Memory Mapped	
	PLL_CORE_MN2DIV	0x0000012C	Memory Mapped	
	PLL_CORE_FRACDIV	0x03000000	Memory Mapped	
	PLL_CORE_BWCTRL	0x00000000	Memory Mapped	
	PLL_CORE_FRACCTRL	0x00000000	Memory Mapped	
	PLL_CORE_STATUS	0xC0000E30	Memory Mapped	
	PLL_CORE_HSDIVIDER	0x00010000	Memory Mapped	
	PLL_CORE_HSDIVIDER_CLKOUT0	0x00000301	Memory Mapped	
	PLL_CORE_HSDIVIDER_CLKOUT1	0x00000302	Memory Mapped	
	PLL_CORE_HSDIVIDER_CLKOUT2	0x00000301	Memory Mapped	
	PLL_CORE_HSDIVIDER_CLKOUT3	0x00000302	Memory Mapped	
	MSS_CR5_CLK_SRC_SEL	0x00000222	Memory Mapped	
	MSS_CR5_DIV_VAL	0x00000000	Memory Mapped	
	SYS_CLK_DIV_VAL	0x00000111	Memory Mapped	
	MSS_CR5_CLK_GATE	0x00000000	Memory Mapped	
	SYS_CLK_GATE	0x00000000	Memory Mapped	
	SYS_CLK_STATUS	0x00000100	Memory Mapped	
	MSS_CR5_CLK_STATUS	0x00000004	Memory Mapped	
	PLL_CORE_RSTCTRL	0x00000000	Memory Mapped	
	PLL_CORE_HSDIVIDER_RSTCTRL	0x00000000	Memory Mapped	
	RSS_CLK_SRC_SEL	0x00000333	Memory Mapped	
	PLLC_CLK2_SRC_SEL	0x00000000	Memory Mapped	
	PLLD_CLK1_SRC_SEL	0x00000000	Memory Mapped	
	PLLD_CLK2_SRC_SEL	0x00000000	Memory Mapped	
	PLLP_CLK1_SRC_SEL	0x00000000	Memory Mapped	
	RSS_DIV_VAL	0x00000000	Memory Mapped	
	RSS_CLK_GATE	0x00000000	Memory Mapped	
	PLLC_CLK2_GATE	0x00000000	Memory Mapped	
	PLLD_CLK1_GATE	0x00000000	Memory Mapped	
	PLLD_CLK2_GATE	0x00000000	Memory Mapped	
	PLLP_CLK1_GATE	0x00000000	Memory Mapped	
	RSS_CLK_STATUS	0x00000008	Memory Mapped	
	PLLC_CLK2_STATUS	0x00000001	Memory Mapped	
	PLLD_CLK1_STATUS	0x00000001	Memory Mapped	
	PLLD_CLK2_STATUS	0x00000001	Memory Mapped	
	PLLP_CLK1_STATUS	0x00000001	Memory Mapped	
	PLL_1P2_HSDIVIDER	0x00010000	Memory Mapped	
	PLL_1P2_HSDIVIDER_CLKOUT0	0x00000004	Memory Mapped	
	PLL_1P2_HSDIVIDER_CLKOUT1	0x00000004	Memory Mapped	
	PLL_1P2_HSDIVIDER_CLKOUT2	0x00000004	Memory Mapped	
	PLL_1P2_HSDIVIDER_CLKOUT3	0x00000305	Memory Mapped	
	PLL_1P2_HSDIVIDER_RSTCTRL	0x00000000	Memory Mapped	
	PLL_1P8_HSDIVIDER	0x00000000	Memory Mapped	
	PLL_1P8_HSDIVIDER_CLKOUT0	0x00000024	Memory Mapped	
	PLL_1P8_HSDIVIDER_CLKOUT1	0x00000024	Memory Mapped	
	PLL_1P8_HSDIVIDER_CLKOUT2	0x00000024	Memory Mapped	
	PLL_1P8_HSDIVIDER_CLKOUT3	0x00000024	Memory Mapped	
	PLL_1P8_HSDIVIDER_RSTCTRL	0x00000000	Memory Mapped	
	PLL_DSP_PWRCTRL	0x00000030	Memory Mapped	
	PLL_DSP_CLKCTRL	0x28134801	Memory Mapped	
	PLL_DSP_TENABLE	0x00000000	Memory Mapped	
	PLL_DSP_TENABLEDIV	0x00000000	Memory Mapped	
	PLL_DSP_M2NDIV	0x00010013	Memory Mapped	
	PLL_DSP_MN2DIV	0x00000168	Memory Mapped	
[100 ... 164]			
	PLL_DSP_FRACDIV	0x03000000	Memory Mapped	
	PLL_DSP_BWCTRL	0x00000000	Memory Mapped	
	PLL_DSP_FRACCTRL	0x00000000	Memory Mapped	
	PLL_DSP_STATUS	0xC0000E38	Memory Mapped	
	PLL_DSP_HSDIVIDER	0x00010000	Memory Mapped	
	PLL_DSP_HSDIVIDER_CLKOUT0	0x00000004	Memory Mapped	
	PLL_DSP_HSDIVIDER_CLKOUT1	0x00000301	Memory Mapped	
	PLL_DSP_HSDIVIDER_CLKOUT2	0x00000302	Memory Mapped	
	PLL_DSP_HSDIVIDER_CLKOUT3	0x00000004	Memory Mapped	
	PLL_PER_PWRCTRL	0x00000030	Memory Mapped	
	PLL_PER_CLKCTRL	0x28135001	Memory Mapped	
	PLL_PER_TENABLE	0x00000000	Memory Mapped	
	PLL_PER_TENABLEDIV	0x00000000	Memory Mapped	
	PLL_PER_M2NDIV	0x00010013	Memory Mapped	
	PLL_PER_MN2DIV	0x00000384	Memory Mapped	
	PLL_PER_FRACDIV	0x08000000	Memory Mapped	
	PLL_PER_BWCTRL	0x00000000	Memory Mapped	
	PLL_PER_FRACCTRL	0x00000000	Memory Mapped	
	PLL_PER_STATUS	0xC0000E38	Memory Mapped	
	PLL_PER_HSDIVIDER	0x00010000	Memory Mapped	
	PLL_PER_HSDIVIDER_CLKOUT0	0x00000308	Memory Mapped	
	PLL_PER_HSDIVIDER_CLKOUT1	0x00000308	Memory Mapped	
	PLL_PER_HSDIVIDER_CLKOUT2	0x00000308	Memory Mapped	
	PLL_PER_HSDIVIDER_CLKOUT3	0x00000308	Memory Mapped	
	PLL_DSP_RSTCTRL	0x00000000	Memory Mapped	
	PLL_DSP_HSDIVIDER_RSTCTRL	0x00000000	Memory Mapped	
	PLL_PER_RSTCTRL	0x00000000	Memory Mapped	
	PLL_PER_HSDIVIDER_RSTCTRL	0x00000000	Memory Mapped	
	ANA_REG_CLK_CTRL_REG1_XO_SLICER	0x00000200	Memory Mapped	
	ANA_REG_CLK_CTRL_REG1_CLKTOP	0x00000007	Memory Mapped	
	ANA_REG_CLK_CTRL_REG2_CLKTOP	0x00000000	Memory Mapped	
	ANA_REG_CLK_CTRL_REG1_LDO_CLKTOP	0x00000001	Memory Mapped	
	ANA_REG_CLK_CTRL_REG2_LDO_CLKTOP	0x00400710	Memory Mapped	
	ANA_REG_CLK_STATUS_REG	0x00000000	Memory Mapped	
	ANA_REG_REFSYS_CTRL_REG_LOWV	0x022080D3	Memory Mapped	
	ANA_REG_REFSYS_TMUX_CTRL_LOWV	0x00000000	Memory Mapped	
	ANA_REG_REFSYS_SPARE_REG_LOWV	0x00000000	Memory Mapped	
	ANA_REG_WU_CTRL_REG_LOWV	0x6076825D	Memory Mapped	
	ANA_REG_WU_TMUX_CTRL_LOWV	0x00000000	Memory Mapped	
	ANA_REG_TW_CTRL_REG_LOWV	0x00000000	Memory Mapped	
	ANA_REG_TW_ANA_TMUX_CTRL_LOWV	0x00000000	Memory Mapped	
	ANA_REG_WU_MODE_REG_LOWV	0x00000004	Memory Mapped	
	ANA_REG_WU_STATUS_REG_LOWV	0x0000BC78	Memory Mapped	
	ANA_REG_WU_SPARE_OUT_LOWV	0x00000029	Memory Mapped	
	HW_SPARE_RW0	0x00000000	Memory Mapped	
	HW_SPARE_RW1	0x00000000	Memory Mapped	
	HW_SPARE_RW2	0x00000000	Memory Mapped	
	HW_SPARE_RW3	0x00000000	Memory Mapped	
	HW_SPARE_RO0	0x00000000	Memory Mapped	
	HW_SPARE_RO1	0x00000000	Memory Mapped	
	HW_SPARE_RO2	0x00000000	Memory Mapped	
	HW_SPARE_RO3	0x00000000	Memory Mapped	
	HW_SPARE_WPH	0x00000000	Memory Mapped	
	HW_SPARE_REC	0x00000000	Memory Mapped	
	LOCK0_KICK0	0x00000000	- KICK0 component  [Memory Mapped]	
	LOCK0_KICK1	0x00000000	- KICK1 component  [Memory Mapped]	
	intr_raw_status	0x00000002	Interrupt Raw Status/Set Register  [Memory Mapped]	
	intr_enabled_status_clear	0x00000000	Interrupt Enabled Status/Clear register  [Memory Mapped]	
	intr_enable	0x00000000	Interrupt Enable register  [Memory Mapped]	
	intr_enable_clear	0x00000000	Interrupt Enable Clear register  [Memory Mapped]	
	eoi	0x00000000	EOI register  [Memory Mapped]	
	fault_address	0x00000040	Fault Address register  [Memory Mapped]	
	fault_type_status	0x00000044	Fault Type Status register  [Memory Mapped]	
	fault_attr_status	0x00000000	Fault Attribute Status register  [Memory Mapped]	
	fault_clear	0x00000000	Fault Clear register  [Memory Mapped]
    Fullscreen MSS_TOPRCM_ES2.0.txt Download 
    [0 ... 99]			
	PID	0x61800214	PID register  [Memory Mapped]	
	HW_REG0	0x00000000	Memory Mapped	
	HW_REG1	0x00000000	Memory Mapped	
	PREVIOUS_NAME	0x00000000	Memory Mapped	
	HW_REG3	0x00000000	Memory Mapped	
	HSI_CLK_SRC_SEL	0x00000333	Memory Mapped	
	CSIRX_CLK_SRC_SEL	0x00000222	Memory Mapped	
	MCUCLKOUT_CLK_SRC_SEL	0x00000000	Memory Mapped	
	PMICCLKOUT_CLK_SRC_SEL	0x00000000	Memory Mapped	
	OBSCLKOUT_CLK_SRC_SEL	0x00000000	Memory Mapped	
	TRCCLKOUT_CLK_SRC_SEL	0x00000000	Memory Mapped	
	CSIRX_DIV_VAL	0x00000111	Memory Mapped	
	MCUCLKOUT_DIV_VAL	0x00000000	Memory Mapped	
	PMICCLKOUT_DIV_VAL	0x00000000	Memory Mapped	
	OBSCLKOUT_DIV_VAL	0x00000000	Memory Mapped	
	TRCCLKOUT_DIV_VAL	0x00000000	Memory Mapped	
	CSIRX_CLK_GATE	0x00000000	Memory Mapped	
	MCUCLKOUT_CLK_GATE	0x00000007	Memory Mapped	
	PMICCLKOUT_CLK_GATE	0x00000007	Memory Mapped	
	OBSCLKOUT_CLK_GATE	0x00000000	Memory Mapped	
	TRCCLKOUT_CLK_GATE	0x00000000	Memory Mapped	
	DSS_CLK_GATE	0x00000000	Memory Mapped	
	HSI_CLK_STATUS	0x00000004	Memory Mapped	
	CSIRX_CLK_STATUS	0x00000104	Memory Mapped	
	MCUCLKOUT_CLK_STATUS	0x00000100	Memory Mapped	
	PMICCLKOUT_CLK_STATUS	0x00000100	Memory Mapped	
	OBSCLKOUT_CLK_STATUS	0x00000001	Memory Mapped	
	TRCCLKOUT_CLK_STATUS	0x00000001	Memory Mapped	
	WARM_RESET_CONFIG	0x00070707	Memory Mapped	
	SYS_RST_CAUSE	0x00000009	Memory Mapped	
	SYS_RST_CAUSE_CLR	0x00000000	Memory Mapped	
	DSS_RST_CTRL	0x00000000	Memory Mapped	
	RS232_BITINTERVAL	0x6C815D5B	Memory Mapped	
	LVDS_PAD_CTRL0	0x00000000	Memory Mapped	
	LVDS_PAD_CTRL1	0x02000000	Memory Mapped	
	DFT_DMLED_EXEC	0x00000000	Memory Mapped	
	DFT_DMLED_STATUS	0x00000000	Memory Mapped	
	LIMP_MODE_EN	0x00000000	Memory Mapped	
	PMICCLKOUT_DCDC_CTRL	0x00000000	Memory Mapped	
	PMICCLKOUT_DCDC_SLOPE	0x00000000	Memory Mapped	
	RCOSC32K_CTRL	0x00000000	Memory Mapped	
	ANA_HSI2DIGCLK_GATE	0x00000007	Memory Mapped	
	PLL_CORE_PWRCTRL	0x00000030	Memory Mapped	
	PLL_CORE_CLKCTRL	0x27134801	Memory Mapped	
	PLL_CORE_TENABLE	0x00000000	Memory Mapped	
	PLL_CORE_TENABLEDIV	0x00000000	Memory Mapped	
	PLL_CORE_M2NDIV	0x00010013	Memory Mapped	
	PLL_CORE_MN2DIV	0x0000012C	Memory Mapped	
	PLL_CORE_FRACDIV	0x03000000	Memory Mapped	
	PLL_CORE_BWCTRL	0x00000000	Memory Mapped	
	PLL_CORE_FRACCTRL	0x00000000	Memory Mapped	
	PLL_CORE_STATUS	0xC0000E30	Memory Mapped	
	PLL_CORE_HSDIVIDER	0x00010000	Memory Mapped	
	PLL_CORE_HSDIVIDER_CLKOUT0	0x00000301	Memory Mapped	
	PLL_CORE_HSDIVIDER_CLKOUT1	0x00000302	Memory Mapped	
	PLL_CORE_HSDIVIDER_CLKOUT2	0x00000301	Memory Mapped	
	PLL_CORE_HSDIVIDER_CLKOUT3	0x00000302	Memory Mapped	
	MSS_CR5_CLK_SRC_SEL	0x00000222	Memory Mapped	
	MSS_CR5_DIV_VAL	0x00000000	Memory Mapped	
	SYS_CLK_DIV_VAL	0x00000111	Memory Mapped	
	MSS_CR5_CLK_GATE	0x00000000	Memory Mapped	
	SYS_CLK_GATE	0x00000000	Memory Mapped	
	SYS_CLK_STATUS	0x00000100	Memory Mapped	
	MSS_CR5_CLK_STATUS	0x00000004	Memory Mapped	
	PLL_CORE_RSTCTRL	0x00000000	Memory Mapped	
	PLL_CORE_HSDIVIDER_RSTCTRL	0x00000000	Memory Mapped	
	RSS_CLK_SRC_SEL	0x00000111	Memory Mapped	
	PLLC_CLK2_SRC_SEL	0x00000000	Memory Mapped	
	PLLD_CLK1_SRC_SEL	0x00000000	Memory Mapped	
	PLLD_CLK2_SRC_SEL	0x00000000	Memory Mapped	
	PLLP_CLK1_SRC_SEL	0x00000000	Memory Mapped	
	RSS_DIV_VAL	0x00000000	Memory Mapped	
	RSS_CLK_GATE	0x00000000	Memory Mapped	
	PLLC_CLK2_GATE	0x00000000	Memory Mapped	
	PLLD_CLK1_GATE	0x00000000	Memory Mapped	
	PLLD_CLK2_GATE	0x00000000	Memory Mapped	
	PLLP_CLK1_GATE	0x00000000	Memory Mapped	
	RSS_CLK_STATUS	0x00000002	Memory Mapped	
	PLLC_CLK2_STATUS	0x00000001	Memory Mapped	
	PLLD_CLK1_STATUS	0x00000001	Memory Mapped	
	PLLD_CLK2_STATUS	0x00000001	Memory Mapped	
	PLLP_CLK1_STATUS	0x00000001	Memory Mapped	
	PLL_1P2_HSDIVIDER	0x00000000	Memory Mapped	
	PLL_1P2_HSDIVIDER_CLKOUT0	0x00000024	Memory Mapped	
	PLL_1P2_HSDIVIDER_CLKOUT1	0x00000024	Memory Mapped	
	PLL_1P2_HSDIVIDER_CLKOUT2	0x00000024	Memory Mapped	
	PLL_1P2_HSDIVIDER_CLKOUT3	0x00000024	Memory Mapped	
	PLL_1P2_HSDIVIDER_RSTCTRL	0x00000000	Memory Mapped	
	PLL_1P8_HSDIVIDER	0x00000000	Memory Mapped	
	PLL_1P8_HSDIVIDER_CLKOUT0	0x00000004	Memory Mapped	
	PLL_1P8_HSDIVIDER_CLKOUT1	0x00000004	Memory Mapped	
	PLL_1P8_HSDIVIDER_CLKOUT2	0x00000004	Memory Mapped	
	PLL_1P8_HSDIVIDER_CLKOUT3	0x00000004	Memory Mapped	
	PLL_1P8_HSDIVIDER_RSTCTRL	0x00000000	Memory Mapped	
	PLL_DSP_PWRCTRL	0x00000030	Memory Mapped	
	PLL_DSP_CLKCTRL	0x27134801	Memory Mapped	
	PLL_DSP_TENABLE	0x00000000	Memory Mapped	
	PLL_DSP_TENABLEDIV	0x00000000	Memory Mapped	
	PLL_DSP_M2NDIV	0x00010013	Memory Mapped	
	PLL_DSP_MN2DIV	0x00000168	Memory Mapped	
[100 ... 164]			
	PLL_DSP_FRACDIV	0x03000000	Memory Mapped	
	PLL_DSP_BWCTRL	0x00000000	Memory Mapped	
	PLL_DSP_FRACCTRL	0x00000000	Memory Mapped	
	PLL_DSP_STATUS	0xC0000E38	Memory Mapped	
	PLL_DSP_HSDIVIDER	0x00010000	Memory Mapped	
	PLL_DSP_HSDIVIDER_CLKOUT0	0x00000004	Memory Mapped	
	PLL_DSP_HSDIVIDER_CLKOUT1	0x00000301	Memory Mapped	
	PLL_DSP_HSDIVIDER_CLKOUT2	0x00000302	Memory Mapped	
	PLL_DSP_HSDIVIDER_CLKOUT3	0x00000004	Memory Mapped	
	PLL_PER_PWRCTRL	0x00000030	Memory Mapped	
	PLL_PER_CLKCTRL	0x27135001	Memory Mapped	
	PLL_PER_TENABLE	0x00000000	Memory Mapped	
	PLL_PER_TENABLEDIV	0x00000000	Memory Mapped	
	PLL_PER_M2NDIV	0x00010013	Memory Mapped	
	PLL_PER_MN2DIV	0x00000384	Memory Mapped	
	PLL_PER_FRACDIV	0x08000000	Memory Mapped	
	PLL_PER_BWCTRL	0x00000000	Memory Mapped	
	PLL_PER_FRACCTRL	0x00000000	Memory Mapped	
	PLL_PER_STATUS	0xC0000E38	Memory Mapped	
	PLL_PER_HSDIVIDER	0x00010000	Memory Mapped	
	PLL_PER_HSDIVIDER_CLKOUT0	0x00000308	Memory Mapped	
	PLL_PER_HSDIVIDER_CLKOUT1	0x00000308	Memory Mapped	
	PLL_PER_HSDIVIDER_CLKOUT2	0x00000308	Memory Mapped	
	PLL_PER_HSDIVIDER_CLKOUT3	0x00000308	Memory Mapped	
	PLL_DSP_RSTCTRL	0x00000000	Memory Mapped	
	PLL_DSP_HSDIVIDER_RSTCTRL	0x00000000	Memory Mapped	
	PLL_PER_RSTCTRL	0x00000000	Memory Mapped	
	PLL_PER_HSDIVIDER_RSTCTRL	0x00000000	Memory Mapped	
	ANA_REG_CLK_CTRL_REG1_XO_SLICER	0x00000200	Memory Mapped	
	ANA_REG_CLK_CTRL_REG1_CLKTOP	0x00000007	Memory Mapped	
	ANA_REG_CLK_CTRL_REG2_CLKTOP	0x00000000	Memory Mapped	
	ANA_REG_CLK_CTRL_REG1_LDO_CLKTOP	0x00000001	Memory Mapped	
	ANA_REG_CLK_CTRL_REG2_LDO_CLKTOP	0x00400710	Memory Mapped	
	ANA_REG_CLK_STATUS_REG	0x00000000	Memory Mapped	
	ANA_REG_REFSYS_CTRL_REG_LOWV	0x022080D3	Memory Mapped	
	ANA_REG_REFSYS_TMUX_CTRL_LOWV	0x00000000	Memory Mapped	
	ANA_REG_REFSYS_SPARE_REG_LOWV	0x00000000	Memory Mapped	
	ANA_REG_WU_CTRL_REG_LOWV	0x6076825D	Memory Mapped	
	ANA_REG_WU_TMUX_CTRL_LOWV	0x00000000	Memory Mapped	
	ANA_REG_TW_CTRL_REG_LOWV	0x00000000	Memory Mapped	
	ANA_REG_TW_ANA_TMUX_CTRL_LOWV	0x00000000	Memory Mapped	
	ANA_REG_WU_MODE_REG_LOWV	0x00000004	Memory Mapped	
	ANA_REG_WU_STATUS_REG_LOWV	0x0000BC78	Memory Mapped	
	ANA_REG_WU_SPARE_OUT_LOWV	0x00000029	Memory Mapped	
	HW_SPARE_RW0	0x00000000	Memory Mapped	
	HW_SPARE_RW1	0x00000000	Memory Mapped	
	HW_SPARE_RW2	0x00000000	Memory Mapped	
	HW_SPARE_RW3	0x00000000	Memory Mapped	
	HW_SPARE_RO0	0x00000111	Memory Mapped	
	HW_SPARE_RO1	0x00000000	Memory Mapped	
	HW_SPARE_RO2	0x00000000	Memory Mapped	
	HW_SPARE_RO3	0x00000000	Memory Mapped	
	HW_SPARE_WPH	0x00000000	Memory Mapped	
	HW_SPARE_REC	0x00000000	Memory Mapped	
	LOCK0_KICK0	0x00000000	- KICK0 component  [Memory Mapped]	
	LOCK0_KICK1	0x00000000	- KICK1 component  [Memory Mapped]	
	intr_raw_status	0x00000002	Interrupt Raw Status/Set Register  [Memory Mapped]	
	intr_enabled_status_clear	0x00000000	Interrupt Enabled Status/Clear register  [Memory Mapped]	
	intr_enable	0x00000000	Interrupt Enable register  [Memory Mapped]	
	intr_enable_clear	0x00000000	Interrupt Enable Clear register  [Memory Mapped]	
	eoi	0x00000000	EOI register  [Memory Mapped]	
	fault_address	0x00000040	Fault Address register  [Memory Mapped]	
	fault_type_status	0x00000044	Fault Type Status register  [Memory Mapped]	
	fault_attr_status	0x00000000	Fault Attribute Status register  [Memory Mapped]	
	fault_clear	0x00000000	Fault Clear register  [Memory Mapped]

    Regards,

    guilin.shi

  • 0 in reply to shi guilin
    TI__Mastermind 35295 points

    Helo Shi guilin,

    You have mentioned that you select one, but according  to your program, the value for the CLK_SRC_SEL is  0x00000222 in both cases.
    Have you made this change purposefully?

    Only difference I see in this code is:


    Also when you say same code you are running in ES 1.0 vs ES 2.0, are you running the same application binary? Also does this application does it have the bss firmware, because es 1.0 and es 20 should have different firmware.
    Unless you are not using the bss in the application

    Regards,
    Saswat Kuamr

  • 0 in reply to Saswat Kumar
    Prodigy 181 points

    Hello Saswat,

    I deliberately set this CLK_SRC_SEL to 2 because DPLL_PER_HSDIV0_CLKCOU2 was originally planned to be used for the clock of CSI2 in the clock tree

    What I mean by running the same program is the following operation：
    1.Burn three files with a script（sbl_qspi.release.tiimage   sbl_uart_uniflash.release.tiimage awr2944_mmw_ti_demoDDM.appimage ）
    2.Debugging and Running My App Program with CCS
    I don't know if BSS is used. I don't know if BSS has any impact on the CSI2 module

    Regards,

    guilin.shi

  • 0 in reply to shi guilin
    TI__Mastermind 35295 points

    Hello Shi guilin,

    So, the appimage you are using across ES 1.0 and ES 2.0 are the same?

    Regards,
    Saswat Kumar

  • 0 in reply to Saswat Kumar
    Prodigy 181 points

    Hello Saswat,

    Yes, both the appimage and the debugging program are the same.

    Regards,

    guilin.shi

  • 0 in reply to shi guilin
    TI__Mastermind 35295 points

    Hello Shi guilin,

    Let's try to change the approach.
    Can you take your old SBL and then make the below changes and try it on the ES 2.0 and then try the application?:

    Regards,
    Saswat Kumar

  • 0 in reply to Saswat Kumar
    Prodigy 181 points

    Hello Saswat,

      Sure, which part of the code do I need to modify for the first modification? （ SBL Loads full BSS RAM image ->   BSS is running from ROM, SBL will load only the patch image）

      Can you tell me which part of the code needs to be modified for the other two modifications? I'm afraid there might be problems caused by my code modifications。

    Regards,

    guilin.shi

  • 0 in reply to shi guilin
    TI__Mastermind 35295 points

    Hello Shi guilin,

    1) The first part is that the app image that is created in the SDK should use the firmware from the DFP present in 4.4.1.2.

    2) and 3) the functions are already mentioned, only in those functions you have to modify.

    You can try it if theres any issue let me know
    Paralelly I am trying to get a setup with the 4.4.1.2 SDK for the ES 2.0, once done I will let you know on that as well( Estimated 2 weeks for setup)

    Regards,
    Saswat Kumar

  • 0 in reply to Saswat Kumar
    Prodigy 181 points

    Hello Saswat,

      Ok, I got it.

    Regards,

    guilin.shi

  • 0 in reply to shi guilin
    Prodigy 181 points

    Hello Saswat,

      Using my old SBL program and modifying ES2.0, the CSI2 module can be used.

      If there are any results from your modifications based on 4.4.1.2 SDK, please update me.
    I can currently use the CSI2 module using the above method.

    Regards,

    guilin.shi

  • 0 in reply to shi guilin
    TI__Mastermind 35295 points

    Hello shi guilin,

    Good to know you have a working solution for now. Currently I am out of office on sick leave, as soon as I get any result in the setup will let you know.

    Regards,

    Saswat Kumar