Hi,
I debugged the CSI2 mode by running it on the AWR 2844 ES1.0.
but when zhe AWR2944 ES1.0 to ES2.0 changes,zhe CSI2 mode cannot receive.
There are no changes related to CSI2 in the modification information from ES1.0 to ES2.0.
May I ask if there is any good solution?
Regards,
guilin.shi
Hello shi,
You have again placed a count for isResetdone, can you remove it and see how long it takes to receive the signal?
If your FPGA works with ES 1.0 then it should be functional with ES 2.0, as there has been no change in CSI2.
CSIRX_complexioIsResetDone fails only if the pins are not getting the transmitted signals. Have you tried with a different EVM or chip?
Are you using the EVM, or your custom board? If it is the EVM, to enable CSI2 there are hardware modifications that need to be done:
By default, there is no CSI2 connection on the EVM you will have to populate those as it is not connected.
Can you check your hardware properly and the EVM as well. As far as I am aware there is nothing changed with the CSI2 IP from ES 1.0 to ES 2.0.
Regards,
Saswat Kumar
Hello Shi,
I had requested for the register values that is present in the CCS in the top right corner under the registers tab itself:
You can copy registers as well in notepad:
In both failing and passing case share me the CSI2, MSS_TOPRCM, MSS_RCM and MSS_CTRL
Direct dump like that it very hard to decode and time consuming as well, I would appreciate if you can give in a format like the registers I have attached below:
RSS_CSI2A RSS CSI2A Module Registers [0 ... 99] CSI2_REVISION 0x00000030 MODULE REVISION This register contains the IP revision code in binary coded digital. For example we have: 0x01 = revision 0.1 and 0x21 = revision 2.1 [Memory Mapped] CSI2_SYSCONFIG 0x00000001 SYSTEM CONFIGURATION REGISTER This register is the OCP-socket system configuration register. [Memory Mapped] CSI2_SYSSTATUS 0x00000001 SYSTEM STATUS REGISTER This register provides status information about the module excluding the interrupt status register. [Memory Mapped] CSI2_IRQSTATUS 0x00000000 INTERRUPT STATUS REGISTER - All contexts This register associates one bit for each context in order to determine which context has generated the interrupt. The context shall be enabled for events to be generated on that context. If the [Memory Mapped] CSI2_IRQENABLE 0x00000000 INTERRUPT ENABLE REGISTER - All contexts This register associates one bit for each context in order to enable/disable each context individually. [Memory Mapped] CSI2_CTRL 0x00000000 GLOBAL CONTROL REGISTER This register controls the CSI2 RECEIVER module. This register shall not be modified dynamically (except IF_EN bit field). [Memory Mapped] CSI2_DBG_H 0x00000000 DEBUG REGISTER (Header) This register provides a way to debug the CSI2 RECEIVER module with no image sensor connected to the module. The debug mode is enabled by CSI2_CTRL.DBG_EN. Only full 32-bit values shall be written. The register is [Memory Mapped] CSI2_GNQ 0x0000001B GENERIC PARAMETER REGISTER This register provide a way to read the generic parameters used in the design. [Memory Mapped] CSI2_COMPLEXIO_CFG2 0x00000000 COMPLEX IO CONFIGURATION REGISTER for the complex IO #2 This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in addit [Memory Mapped] CSI2_COMPLEXIO_CFG1 0x00000000 COMPLEXIO CONFIGURATION REGISTER for the complex IO #1 This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in additi [Memory Mapped] CSI2_COMPLEXIO1_IRQSTATUS 0x00000000 INTERRUPT STATUS REGISTER - All errors from complex IO #1 [Memory Mapped] CSI2_COMPLEXIO2_IRQSTATUS 0x00000000 INTERRUPT STATUS REGISTER - All errors from complex IO #2 [Memory Mapped] CSI2_SHORT_PACKET 0x00000000 SHORT PACKET INFORMATION - This register sets the 24-bit DATA_ID + Short Packet Data Field when the data type is between 0x8 and x0F [Memory Mapped] CSI2_COMPLEXIO1_IRQENABLE 0x00000000 INTERRUPT ENABLE REGISTER - All errors from complex IO #1 [Memory Mapped] CSI2_COMPLEXIO2_IRQENABLE 0x00000000 INTERRUPT ENABLE REGISTER - All errors from complex IO #2 [Memory Mapped] CSI2_DBG_P 0x00000000 DEBUG REGISTER (Payload) This register provides a way to debug the CSI2 RECEIVER module with no image sensor connected to the module. The debug mode is enabled by CSI2_CTRL.DBG_EN. Only full 32-bit values shall be written. The register is [Memory Mapped] CSI2_TIMING 0x7FFF7FFF TIMING REGISTER This register controls the CSI2 RECEIVER module. This register shall not be modified while CSI2_CTRL.IF_EN is set to '1'. It is used to indicate the number of L3 cycles for the Stop State monitoring. [Memory Mapped] CSI2_CTX0_CTRL1 0x00010008 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX0_CTRL2 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORMAT ha [Memory Mapped] CSI2_CTX0_DAT_OFST 0x00000000 DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR. [Memory Mapped] CSI2_CTX0_DAT_PING_ADDR 0x00000000 DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX0_DAT_PONG_ADDR 0x00000000 DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX0_IRQENABLE 0x00000000 INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX0_IRQSTATUS 0x00000000 INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX0_CTRL3 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX1_CTRL1 0x00010008 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX1_CTRL2 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORMAT ha [Memory Mapped] CSI2_CTX1_DAT_OFST 0x00000000 DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR. [Memory Mapped] CSI2_CTX1_DAT_PING_ADDR 0x00000000 DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX1_DAT_PONG_ADDR 0x00000000 DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX1_IRQENABLE 0x00000000 INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX1_IRQSTATUS 0x00000000 INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX1_CTRL3 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX2_CTRL1 0x00010008 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX2_CTRL2 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORMAT ha [Memory Mapped] CSI2_CTX2_DAT_OFST 0x00000000 DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR. [Memory Mapped] CSI2_CTX2_DAT_PING_ADDR 0x00000000 DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX2_DAT_PONG_ADDR 0x00000000 DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX2_IRQENABLE 0x00000000 INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX2_IRQSTATUS 0x00000000 INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX2_CTRL3 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX3_CTRL1 0x00010008 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX3_CTRL2 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORMAT ha [Memory Mapped] CSI2_CTX3_DAT_OFST 0x00000000 DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR. [Memory Mapped] CSI2_CTX3_DAT_PING_ADDR 0x00000000 DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX3_DAT_PONG_ADDR 0x00000000 DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX3_IRQENABLE 0x00000000 INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX3_IRQSTATUS 0x00000000 INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX3_CTRL3 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX4_CTRL1 0x00010008 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX4_CTRL2 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORMAT ha [Memory Mapped] CSI2_CTX4_DAT_OFST 0x00000000 DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR. [Memory Mapped] CSI2_CTX4_DAT_PING_ADDR 0x00000000 DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX4_DAT_PONG_ADDR 0x00000000 DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX4_IRQENABLE 0x00000000 INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX4_IRQSTATUS 0x00000000 INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX4_CTRL3 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX5_CTRL1 0x00010008 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX5_CTRL2 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORMAT ha [Memory Mapped] CSI2_CTX5_DAT_OFST 0x00000000 DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR. [Memory Mapped] CSI2_CTX5_DAT_PING_ADDR 0x00000000 DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX5_DAT_PONG_ADDR 0x00000000 DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX5_IRQENABLE 0x00000000 INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX5_IRQSTATUS 0x00000000 INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX5_CTRL3 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX6_CTRL1 0x00010008 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX6_CTRL2 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORMAT ha [Memory Mapped] CSI2_CTX6_DAT_OFST 0x00000000 DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR. [Memory Mapped] CSI2_CTX6_DAT_PING_ADDR 0x00000000 DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX6_DAT_PONG_ADDR 0x00000000 DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX6_IRQENABLE 0x00000000 INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX6_IRQSTATUS 0x00000000 INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX6_CTRL3 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX7_CTRL1 0x00010008 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX7_CTRL2 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORMAT ha [Memory Mapped] CSI2_CTX7_DAT_OFST 0x00000000 DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR. [Memory Mapped] CSI2_CTX7_DAT_PING_ADDR 0x00000000 DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX7_DAT_PONG_ADDR 0x00000000 DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX7_IRQENABLE 0x00000000 INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX7_IRQSTATUS 0x00000000 INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX7_CTRL3 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_PHY_CFG_REG0 0x00000000 Memory Mapped CSI2_PHY_CFG_REG1 0x00000000 Memory Mapped CSI2_PHY_CFG_REG2 0x00000000 Memory Mapped CSI2_PHY_CFG_REG3 0x00000000 Memory Mapped CSI2_PHY_CFG_REG4 0x00000000 Memory Mapped CSI2_PHY_CFG_REG5 0x00000000 Memory Mapped CSI2_PHY_CFG_REG6 0x00000000 Memory Mapped CSI2_CTX0_TRANSCODEH 0x00000000 Transcode configuration register: defines horizontal frame cropping [Memory Mapped] CSI2_CTX0_TRANSCODEV 0x00000000 Transcode configuration register: defines vertical frame cropping [Memory Mapped] CSI2_CTX1_TRANSCODEH 0x00000000 Transcode configuration register: defines horizontal frame cropping [Memory Mapped] CSI2_CTX1_TRANSCODEV 0x00000000 Transcode configuration register: defines vertical frame cropping [Memory Mapped] CSI2_CTX2_TRANSCODEH 0x00000000 Transcode configuration register: defines horizontal frame cropping [Memory Mapped] CSI2_CTX2_TRANSCODEV 0x00000000 Transcode configuration register: defines vertical frame cropping [Memory Mapped] CSI2_CTX3_TRANSCODEH 0x00000000 Transcode configuration register: defines horizontal frame cropping [Memory Mapped] CSI2_CTX3_TRANSCODEV 0x00000000 Transcode configuration register: defines vertical frame cropping [Memory Mapped] CSI2_CTX4_TRANSCODEH 0x00000000 Transcode configuration register: defines horizontal frame cropping [Memory Mapped] CSI2_CTX4_TRANSCODEV 0x00000000 Transcode configuration register: defines vertical frame cropping [Memory Mapped] CSI2_CTX5_TRANSCODEH 0x00000000 Transcode configuration register: defines horizontal frame cropping [Memory Mapped] CSI2_CTX5_TRANSCODEV 0x00000000 Transcode configuration register: defines vertical frame cropping [Memory Mapped] [100 ... 103] CSI2_CTX6_TRANSCODEH 0x00000000 Transcode configuration register: defines horizontal frame cropping [Memory Mapped] CSI2_CTX6_TRANSCODEV 0x00000000 Transcode configuration register: defines vertical frame cropping [Memory Mapped] CSI2_CTX7_TRANSCODEH 0x00000000 Transcode configuration register: defines horizontal frame cropping [Memory Mapped] CSI2_CTX7_TRANSCODEV 0x00000000 Transcode configuration register: defines vertical frame cropping [Memory Mapped]
Regards,
Saswat Kumar
Hello Shi guillin,
Why is there a change in the configuration of the phy registers:
Regards,
Saswat Kumar
Hello Shi,
Thanks for what you have shared but this is not the entire list: 
You have only sent 0-99 for each also.
Also Please just update it into a es1reg.txt and es2reg.txt file like I have attached here:
You can see below that I just dragged and dropped the sample.txt file, it will keep this entire conversation in one page then.
In both failing and passing case share me the CSI2, MSS_TOPRCM, MSS_RCM and MSS_CTRL
Direct dump like that it very hard to decode and time consuming as well, I would appreciate if you can give in a format like the registers I have attached below:
Regards,
Saswat Kumar
Hello shi guillin,
Looks like from this register comparison:
Your hsdiv 0,2,3 clockouts for per pll and some for DSP are also powered down.
Can you check what you are using as the clock source for CSI2 and which divider and what value as well?
Regards,
Saswat Kumar
Hello Shi guilin,
Are you feeding any external clock to CSI2?
in your MSS_TOPRCM es 2.0 the
CSIRX_CLK_SRC_SEL 0x00000000 Memory Mapped
Which means from TRM you are using:
Please select a valid source for this as well, and modify it accordingly in the SBL where it does the clock.
As in es 1 SDK the unconfigured clock sources were not gated but in case of ES 2.0 we are gating the unconfigured clock sources.
Regards,
Saswat Kumar
Hello Saswat,
I tried to modify the clock configuration in Bootloader_socConfigPll. However, it often causes DSS to fail to start or programs to fail to run. As shown in the figure below
Excuse me, is the clock configured here? Do you have any good configuration plans?
Regards,
guilin.shi
Helo Shi guillin,
Yes the clocks are configured here, instead of changing the clock values, change the clock src to one of the dividers and then just ungate the divider by writing this for example:
So for whichever clock you are selecting as source for the CSIRX CLK SRC SEL:
Regrads,
Saswat Kumar
Hello Saswat,
I configure the clock source through the following code.
==========
==========
I can see through CCS that the value of the register has been modified to the value I set. But CSI2 init still cannot succeed.
Regards,
guilin.shi
Hello Shi guilin,
Here your clk_src_sel is 0x222
Which means from this diagram
So for whichever clock you are selecting as source for the CSIRX CLK SRC SEL:
YOu are selecting PER_HSDIV0_CLKOUT2
In the logs you have sent:
PLL_PER_HSDIVIDER_CLKOUT2 0x00001004 Memory Mapped
In this the 12th bit: PLL_PER_HSDIVIDER_CLKOUT2_PWDN is 1 which means CLKOUT2 divider is powered down
Also I noticed and error here:
/* Configure CLKOUT1 to DSS PLL Fout/2. Divider is hsDivOut + 1 so set 1 */hsDivCfg.hsDivOutFreqHz[1] = SOC_RCM_FREQ_MHZ2HZ(360U);hsDivCfg.hsDivOutFreqHz[2] = SOC_RCM_FREQ_MHZ2HZ(240U);SOC_rcmDspPllConfig(SOC_RcmPllFoutFreqId_CLK_720MHZ, &hsDivCfg);retVal = SOC_rcmSetHSDivMux(SOC_RcmHSDIVClkOutMuxId_DPLL_DSP_OUT1,SOC_RcmHSDIVClkOutMuxClockSource_DPLL_DSP_HSDIV0_CLKOUT1_PreMux);DebugP_assert(retVal == SystemP_SUCCESS);retVal = SOC_rcmSetHSDivMux(SOC_RcmHSDIVClkOutMuxId_DPLL_DSP_OUT2,SOC_RcmHSDIVClkOutMuxClockSource_DPLL_DSP_HSDIV0_CLKOUT2_PreMux);unsigned int* p1 = (unsigned int*)0x02140018u;
You are configuring for DSP_PLL not the PER_PLL you want to use for.
Regards,
Saswat Kumar
Hello Saswat,
Sorry, I've been busy with other things lately and haven't updated on this issue.
I want to configure the CSI2 clock through a clock tree file.
Because PER_PLL_HSDIV0_CLKOUT1 is currently in use, I understand that I only need to configure the values of M6 and GATE_CTRL for clock PER_PLL_HSDIV0_CLKOUT2.Set up through the following code.
But this value has always been 1（PLL_PER_HSDIVIDER_CLKOUT2_PWDN is 1）.
============
============
Regards,
guilin.shi
