Dear engineers:
Hello!
We use four AWR2243 chips for cascade design. Now we encounter a problem. When we send a reset signal to the AWR2243 through the FPGA, the SPI_HOST_INTR pin of the AWR2243 is not pulled high. It is always at a low level.
We checked that the power supply voltage of AWR2243 is normal, the crystal oscillator signal is normal, the reset signal is normal, the NERROR_OUT pin is also high level, and the SOP mode is SOP4 mode.
Our workflow is to first control the PMIC to power the AWR2243 through the FPGA, and then enable the reset signal. However, when we enable the reset signal, we observe that the overall current of our board does not fluctuate much. Although we have checked that the reset signal can be pulled low and then high, we are not sure whether the AWR2243 has started normally because the current fluctuation is very small.
Our above test is only for the master AWR2243. The slave AWR2243 has not been tested yet. It is worth noting that the VIO pin of our AWR2243 is connected to 1.8V.
How can we troubleshoot the problem? Thanks.
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