Dear engineers:
Hello!
We use AWR2243 for four-chip cascade design. We designed a separate FPGA core board (using Xilinx's ZU5EG). Currently we have encountered some problems and want to consult:
1. When FPGA and AWR2243 communicate using SPI, FPGA first sends a reset signal to AWR2243. According to the normal process, AWR2243 will reply to FPGA with a high-level IRQ signal, that is, SPI_HOST_INTR will change from low to high, but we do not To capture the change of this signal, IRQ is always low. Does the successful handshake between FPGA and AWR2243 only require the FPGA to give a reset signal to AWR2243? Does the FPGA need to send other signals to the AWR2243 before the IRQ becomes high?
2. AWR2243 SOP mode We use SOP4 mode (SOP0=1, SOP1=0, SOP2=0). We use resistors to set this working mode. There is no need to control it through FPGA pins. Is this design feasible? ?
3. After powering on the board, we found that the current fluctuation is very small. We are not sure how to judge the status of the AWR2243 from the hardware when there is no program running, or how to judge whether the hardware design or chip of the AWR2243 is in a normal state? We have currently tested that the power supply of the chip is correct, the crystal oscillator signal is correct, NEER OUT is high level, and the reset signal is also high level. We currently have no other way to determine whether AWR2243 is in a normal state.
Best Regards,
