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TMAG5170-Q1: CRC operation

Jonathan Jank
Intellectual 1015 points
Part Number: TMAG5170-Q1

Please confirm our understanding of the CRC:

  1. For a regular register read, if the CRC sent to the chip is incorrect, the chip inverts the LSBit of the CRC in the response data. The response data is present, but the CRC miss-matches because the LSBit has been inverted.
  2. For a register write, if the CRC sent to the chip is incorrect, the data is not written to the register. The response data is present, but the CRC miss-matches because the LSBit has been inverted.

thanks,

JJ

  • 0
    TI__Genius 17480 points

    Jonathan,

    Thanks for reaching out. For any transaction if the device detects an error in the received CRC code from the MCU, it will invert the last bit of the CRC transmitted back.  This provides an immediate feedback for the MCU that the CRC fault occurred.  On the subsequent transaction, the CRC fault bit (MSB) will also be toggled to indicate an error in the previous communication packet.

    If this was during a write, then the device will not latch the input data, and the device will remain in its previous state.

    Thanks,

    Scott