Other Parts Discussed in Thread: IWR6843
Hi Team,
We are trying to implement the Playback of raw ADC data via DMM interface in IWR6843ISK using FPGA board.
Reference to this query: https://e2e.ti.com/support/sensors-group/sensors/f/sensors-forum/861828/iwr6843isk-dmm-interface-pin-muxing#pi320995=2
Reference document: /cfs-file/__key/communityserver-discussions-components-files/1023/DMM_5F00_Configuration_5F00_Psudo_5F00_code_5F00_rev2.pdf
1. Unable to understand the steps 5, 6, 7, 15, 16, 17 in the pseudo code. Attached code for your reference.
1. DMM1_TRACE_WRITE (DEST0, 0xFF73C, 0x5000_xxxx)
2. DMM1_TRACE_WRITE (DEST0, 0xFF740, 0x9)
3. DMM1_TRACE_WRITE (DEST0, 0xFF74C, 0xFFFF_xxxx)
4. DMM1_TRACE_WRITE (DEST0, 0xFF750, 0x9)
/* Configuring PING buffer */
/* PING value , 0x420000
PONG value 0x634000 */
Current buffer = PING
5. DMM1_TRACE_WRITE (DEST1, 0x660, Current buffer)
/* 2 idle clock cycles would be required */
/* (Set Ping pong interrupt Sel and frame start interrupt sel) */
6. DMM1_TRACE_WRITE (DEST2, 0xFF954, 0x880)
/* (Set Frame start interrupt) */
7. DMM1_TRACE_WRITE (DEST2, 0xFF94C, 0x080)
/* 2 idle clock cycles would be required */
/* DMM2 reset */
8. DMM2_WRITE (0xFCFFF600, 0x00010000)
9. DMM2_WRITE (0xFCFFF600, 0x00000000)
/* DMM2 Configuration in Functional Mode */
10. DMM2_WRITE (0xFCFFF66C, 0x0007FFFF)
11. DMM2_WRITE (0xFCFFF68C, 0x0007FFFF)
/* DMM2 Configuration in DDM Mode 32 DDM_WIDTH assumed */
12. DMM2_WRITE (0xFCFFF600, 0x0004050A)
/* configure ADC buffer with the fixed block size of 32k for each chirip */
• ADDR:DDMDEST -> DATA: 0x5209_xxxx
• ADDR:DDMBL -> DATA: 0xB
13. DMM1_TRACE_WRITE (DEST0, 0xFF61C, 0x52090000)
14. DMM1_TRACE_WRITE (DEST0, 0xFF620, 0xB)
/* Now as there is a transition from Trace to DDM mode, 2 idle clock cycles would be required.
DMM_MUX (PAD_BC) should be driven to value “1” to use DMM2 (Direct data Mode).
After this activity transfer data
/* Now as there is a transition from DDM to TRACE mode, 2 idle clock cycles would be required.
DMM_MUX (PAD_BC) should be driven to value “0” to use DMM1 (Trace mode).
/* If the current buffer = PING next buffer = Pong
Else next buffer =PING
/* Configuring PONG buffer */
15. DMM1_TRACE_WRITE (DEST1, 0x660, NEXT Buffer)
Current buffer =Next Buffer
/* The PING PONG interrupt is set to give the Chirp Available Interrupt by writing to the following register using the DMM1 trace mode with DEST2 to indicate that one chirp data is available for processing */
/* Set Ping pong interrupt Sel */
16. DMM1_TRACE_WRITE (DEST2, 0xFF954, 0x880)
/* Set Ping pong interrupt */
17. DMM1_TRACE_WRITE (DEST2, 0xFF94C, 0x800)
/* Add inter chip data/delay if needed */
/* At each chirp repeat the above steps from 8 using the DMM interface until the entire frame data is transferred. */
/* After all the chirps have been transferred add inter frame data/delay if needed */
/* And at each frame repeat the above steps from 6 using the DMM interface until the entire data is transferred. */a
1a. What is the 32 bit address for Step 5, 6, 7, 15, 16, 17 ?
1b. For setting the ping/pong interrupt and frame start interrupt, which register needs to be configured?
1c. Why is the base address written in the block size register in the Configuring PING buffer step?
1d. ADC Buffer PING Base Address is given as 0x52000000. But 0x52000000 is reserved as per the TRM.
2. In DMMGLBCTRL register, what happens when we write Ah and 5h into the LSB 4 bits?
3. Explain indetail the flow need to be followed to implement DMM interface.
Attached Analysis sheet for your reference.
IWR6843_DMM_analysis_sheet.xlsx
Regards
Mohan
