Other Parts Discussed in Thread: IWR1843
Tool/software:
We're utilizing the IWR6843 chip, but we've hit a barrier where we can't surpass 512 chirp loops within a single chirp cycle time. Our priority is to maximize the number of chirp loops, while the number of samples per chirp, which we've found 128 to be sufficient, isn't as critical. How can we configure this setup to meet our requirements? Despite testing both your demo code and our proprietary code, we haven't been able to exceed the following configuration:
chirpCfg 0 0 0 0 0 0 0 1
chirpCfg 1 1 0 0 0 0 0 1
frameCfg 0 1 256 0 500 1 0
We appreciate any guidance you can provide to achieve our desired configuration.