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TMAG5170: [FAQ] TMAG5170 SPI Communication STAT3(ERROR_STAT) Related

donghyuk lee
Prodigy 10 points
Part Number: TMAG5170


Tool/software:

I am sending an inquiry because ERROR_STAT occurred while checking SPI communication using TMAG5170.

An initial CRC disable command was sent (0x0F000407), followed by a command to read the TEST_CONFIG register (0x8F000000).

I am attaching a screenshot of the oscilloscope.

Regular 32-Bit SDO Read Value : 0x6000008C

                                                      STAT10(CFG_RESET), STAT9(ALRT_STATUS1), STAT3(ERROR_STAT) is High.

1. Having trouble sending commands via MOSI?

2. Can I determine that the STAT10(CFG_RESET) bit changing to High is a power supply problem?

3. In the Regular 32-Bit SDO Read signal received from MISO, STAT9 -> 0x1, STAT8 -> 0x0 were confirmed. So ALRT_STATUS is 0x10.

In this case, since the ALRT_STATUS bits (1:0) of the CONV_STATUS register are 0x10, it is confirmed as a SYS Status Flag Set. Can you tell which flag of SYS_STATUS is set?

4. Additionally, can you tell me in detail what error ERROR_STAT, the STAT3 bit, represents in the Regular 32-Bit SDO Read signal?

  • 0
    TI__Mastermind 26335 points

    Hello donghyuk,

    CFG_RESET indicates the hardware has been reset after a power down.  Reading the AFE_STATUS register should clear that bit.

    The Error stat bit indicates there is an error internally (AFE) or externally with the system (SYS). In your case, ALRT_STATUS1 is set high while ALRT_STATUS0 is low, indicating ALRT_STARTUS 1-0 in the CONV_STATUS register is 2h corresponding to system issue.  Reading the SYS_STATUS register will help narrow in on whether it is an issue with the data line, the crc value, the frame, or VCC level.  Per the scope shot you provided, its possible that the issue resides with the frame.  It looks like CS remains low for 64 bits. Pulling CS high at the end of a frame and pulling low again for the next frame, might help with your issue.  If that does not fix your issue, please provide a scope shot of a read back of the SYS_STATUS register.

  • 0 in reply to Patrick Simmons
    Prodigy 10 points

    Hello, Patrick.

    I confirmed that the CRC Disable bit in the TEST_CONFIG register changes to High by modifying the SPI Mode and CS.

    I confirmed that the SYS status flag was set through STAT9 and STAT8 in the Regular 32-Bit SDO signal.

    As a result of checking the SYS_STATUS register, FRAME_STAT is being read as High.

    I would like to inquire if there is a problem with the clock in the attached photo. Additionally, I would like to know how to clear the SYS_STATUS register.

  • 0 in reply to donghyuk lee
    TI__Mastermind 26335 points

    Hey Donghyuk,

    Thanks for providing those details, I will try to have an update later today.

  • 0 in reply to Patrick Simmons
    TI__Mastermind 26335 points

    Hey Donghyuk,

    It looks like you have the clock polarity set such that that line is held high between transmissions.  Per figures 7-14 and 7-15 in the datasheet, I think you should have the clock polarity set such that the line is held low between transmissions.

    If you correct the clock polarity and assuming all specifactions in datasheet table 6.8 are observed, you might fix the frame stat error and then all flags in your sys status register might be cleared.

  • 0 in reply to Patrick Simmons
    Prodigy 10 points

    After correcting the clock polarity, CRC was disabled and register read was confirmed normally. Thank you.

    Additionally, I would like to read conversion information for the X axis. (0x9 register)

    Is there a register that needs to be set to precedence in order to read x-axis conversion data?

  • +1 in reply to donghyuk lee
    TI__Mastermind 26335 points

    Hey Donghyuk,

    To get x-axis information, you will need to set some bits under the MAG_CH_EN in the SENSOR_CONFIG register.  You might also want to change the X_Range bits in that register in case your field range exceeds the default setting.