Tool/software:
Hello TI Team,
Please clarify with below question on the errata MSS#61.
Reference: "AWR294x Device Errata Silicon Revisions 1.0, 2.0" / "SWRZ102B – NOVEMBER 2021 – REVISED OCTOBER 2023"
MSS#61 states " Data aborts seen while access made to last 24 bytes of the configured MPU region and cache is enabled."
1) Is this issue only for MSS?
2) Can similar issue occur with DSS Cache configuration?
Thanks,
BC