Tool/software:
Hi, support
The text in the image states that the DIN: SCLK rising edge, DOUTx: SCLK falling edge. Is this referring to the setup time?
Could you please provide a more detailed explanation to help me understand this better? When does DOUT need to capture the data, thank you
Thank you.
Thank you for reaching out with your question. There are some more details regarding SPI in section 7.5
The plot shared by you above doe have several markings, and these are referenced in Section 6.6
Based on the diagram, it appears data is shifted out on DOUT at the falling edge, and t9 dictates the time from the falling edge until the output should be valid (12ns). Based on this, it would likely be easiest to latch read data on the rising clock edge, provided there is at least 12ns from the falling edge until the subsequent rising edge.
Thanks,
Scott
