MMWCAS-DSP-EVM: FPGA HDL source code

I found the following response. Surely the source code is kept by Ti, since the FPGA is interfacing with a Ti chip? https://e2e.ti.com/support/sensors-group/sensors/f/sensors-forum/1164093/mmwcas-dsp-evm-fpga-source-code

I see that many posts of the same nature are met with the same response as the link in my previous reply, aside from this one. Please share the details that were shared with this user. Thanks.

e2e.ti.com/.../mmwcas-dsp-evm-where-can-i-find-the-binary-code-for-programming-the-4-fpga-on-mmwcas-dsp-evm

Hello,

It was basically the out of box Lattice CSI2 > Parallel Port example project that comes with their Lattice Diamond SDK/IDE tool. I think we just added the specific CSI input, VIN output, and reset pin mapping we wanted on top of this.

Regardless, I do not recommend you to invest any effort into developing anything with the TDA2 design. TI does not even produce this processor that was used for this board anymore, so you will not be able to design a system around this. 

Regards,

Adrian

Thank you for your response.

I wanted this information as I plan on using my own processor/SoC system instead of the TDA2, so it would save some time if I could copy the HDL for interfacing with the AWR2243 chips. Do you have any reference code for this purpose, or should I just use the AWR2243 datasheet? It would be nice if there was an example somewhere showing a simple processor/FPGA to AWR2243 interface.

I see that Xilinx provides CSI-2 Rx and Tx IP cores which could be used to interface with the AWR2243 chips, so the bridge is not necessary if a Xilinx FPGA is used.