AWR6843: AWR6843

Hi,

A HW expert will be following up in the next day or so.

Thanks,

Clinton

Hi Kim,

Can you please share the details about the breakout board which you have mentioned. The layout guidelines including line width can be decided based on the layer stackup.

Regards,

Sreedeep

Hi Sreedeep,

Thanks for your response.

For example, when we should route 270um width for 50 ohm impedance. But it can't be implemented, because pitch to pitch's gap is 650um.

That case, how to route the line which is for passing between ball and ball? wider is better? or is there some target impedance TI recommended?

Thanks,

Hi Kim,

Can you please refer to the below PCB design guide. Do let me know if you have further queries.

TI mmWave Radar sensor RF PCB Design, Manufacturing and Validation Guide

Regards,

Sreedeep

Hi, Sreedeep,

Thanks for your reply.

I reviewed the document you were shared.

But, I don't understand this guide clearly.

How can route the signal line? Maybe there is another ball like red circle.

I want to assume more detail. When we want to use AWR6843, P11 ball as QSPI CS line, we should match the line for 50 ohm.

And, our stack-up guide the line should be routed 270um for 50 ohm impdedance. But it can't be implemented, because pitch to pitch's gap is 650um.

That case, how to route the line which is for passing between ball and ball? wider is better? or is there some target impedance TI recommended?

Thanks,

Hi Kim,

Thanks for clarifying your question.

What we do in our EVM design is that we fan out the QSPI lines from the BGA with a reduced trace width of 4mils and once it is outside the package boundary we will get more space to assign more width. The trace should be ideally matched to 50ohm impedance but due to limitations it can go little higher and be around 60ohms.

Please let me know if you have any doubts.

Regards,

Sreedeep

Please find a snap of the trace routing from P11 CS line

Thanks,

Sreedeep

Hi, Sreedeep.

Thanks for your kind reply.

In TI EVM, what's the impedance of P11 CS line when route 4mil? why CS line's width was designed as 4mil?

Thanks,

Hi Kim,

The trace width is 4mils when it starts from BGA to have:  - good isolation from the other lines 

                                                                                             - 4 mils or 0.1mm is the manufacturing limit by the PCB fabricators.

Once the trace gets outside the package boundary, the thickness changes to 6mils as shown in the snap below. This combined trace would provide approximately an impedance of 50-55 ohms. The PCB material used in our EVM is RO4835LoPro.

Regards,

Sreedeep

Hi, Sreedeep,

Thanks for your reply.

You mean, 6mills line's impedance is 50-55 ohm and 4 mills is the manufaturing limit?

Or the all trace has impedance of 50-55ohm? How to get the impedance? Doing simulation?

Generally, satck-up give the imformation like below

(Top - 6mills : 50 ohm...)

Thanks,

Hi Kim,

The calculations give the 6mil line impedance to be approximately 50ohms. The 4mills (manufacturing limit) line has an impedance of approximately 60ohms. So, both the traces combined should effectively show an impedance around 55ohms. This can be further verified by simulations.

Regards,

Sreedeep