Tool/software:
Hi There,
I am posting this for TI customer. Could you please advise?
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My name is Kris and I work at (...) in the FPGA design team. We are working on developing code to work with the TMP451 part (PN TMP451AQDQWRQ1) and had a few questions on the datasheet.
Datasheet: TMP451-Q1 - SLOS877C – OCTOBER 2014 – REVISED APRIL 2021
Are you able to get in touch with someone that supports that product line?
We are essentially trying to understand if the part supports burst reads/writes as relating to the pointer register operation.
In section 7.5.1.2 there is a statement:
“The number of data bytes transferred between a start and a stop condition is not limited and is determined by the master device. The receiver acknowledges data transfer.”
Is the statement above saying we can burst and the pointer auto increments? Or is that statement just to say that the command and data structure can be of variable length in the interface specification in general. (but its locked to a fixed width defined by the other sections of the datasheet?)
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