Tool/software:
Hi, TI support:
As I know, if the access is to same bank of DSS L3, then there will be arbitration in the BUS and will be on a first come first serve basis. The second requester will be stalled by the bus logic.
R5 and DSP cannot simultaneously access the same data on L3. What is the granularity of this data mutex? For example, if there is 200KB of data on L3, when R5F performs a memcpy of this 200KB data to MSS_L2, does the DSP lose access to this 200KB data for the entire duration of the memcpy? Or does the R5F release the bus briefly after copying each 128 bytes (cache line size), allowing the DSP to update part of the data?
