AWR2243: 20GHz LO signal line (strip line) and GCPW Wilkinson power divider transform via structure

Bo Zhang

Part Number: AWR2243

Tool/software:

Dear TI experts,

We encountered an issue during the development of the AWR2243 cascaded version:

In the tidm464 layout of the AWR2243 Cascade, it is shown that the 20GHz LO strip line is connected to the GCPW Wilkinson power divider through a through-hole. I simulated the connection structure in HFSS using the size of the tidm464 layout and found that the impedance matching was poor (S11 was only -1.1dB).

For this situation, in SPRR407 (detailed schematic of design layout and components), it is written that "In the EVM design for SYNC trace transition being a blind via back drill was drom from TOP to L3". Here, it is said that the signal line transform via is formed as a blind hole through back drilling. Does the actual EVM use blind holes? If the through-hole is turned into a blind hole through back drilling, please provide reference back drilling size and back drilling stub length parameters?

4 months ago

0 aozer 4 months ago

TI__Mastermind 26985 points

Hello,

Yes, back drilling is used. You can see in note 5 of the fab notes in the design files. In this case a 24mil drill bit is used for back drilling for layers 8 through 4.

I do not have details on worst case stub analysis since this was probably done with vendor during initial prototyping and the engineer involved with this design is no longer on the radar team. Based on stack up I would worst case if they stop drilling at L4 you would have a stub of 10.7+0.6mils = 11.3mils.

Regards,

Adrian

0 Bo Zhang 4 months ago in reply to aozer

Prodigy 20 points

Hi,

Thank your reply. I'll try that.

Regards

+1 Bo Zhang 4 months ago in reply to aozer

Prodigy 20 points

Hi,

Thank you, this has been very helpful to me. Can you provide me with a reference file for the TABLE

0 aozer 4 months ago in reply to Bo Zhang

TI__Mastermind 26985 points

Hello,

The stack up table is found in the layout file.

https://www.ti.com/tool/MMWCAS-RF-EVM?utm_source=google&utm_medium=cpc&utm_campaign=epd-null-null-GPN_EN_EVM-cpc-evm-google-wwe&utm_content=MMWCASRFEVM&ds_k=MMWCAS-RF-EVM&DCM=yes&gad_source=1&gclid=CjwKCAjwufq2BhAmEiwAnZqw8utYpTSb76oRmlxNZSH80_NfZNbrjL-8ID0RbwMkxzp_ZOboDkpOzhoCtSIQAvD_BwE&gclsrc=aw.ds#design-files

Regards,

Adrian

0 Bo Zhang 4 months ago in reply to aozer

Prodigy 20 points

Thanks

0 Bo Zhang 4 months ago in reply to aozer

Prodigy 20 points

Hello,

In this stack up table ,the thickness of RO4450F is 5mil, but Rogers datasheet of RO4450F shows that its standard thickness is 4mil, how to get a 5mil thickness RO4450F?

Regards

0 aozer 3 months ago in reply to Bo Zhang

TI__Mastermind 26985 points

Hello,

As mentioned by Rogers, you or your contract manufacturer need to reach out to them directly for different configurations. Although 4mil is the standard thickness they can provide additional options.

Regards,

Adrian

0 Bo Zhang 3 months ago in reply to aozer

Prodigy 20 points

Hello,

Can the GCPWs(20GHz LO input and output paths) from the chip share a row of vias? What is the isolation requirement for these two channels?

Regards

0 aozer 3 months ago in reply to Bo Zhang

TI__Mastermind 26985 points

Hello,

We have not validated this on our end so I cannot definitively say whether this will be ok or not. I would recommend avoiding doing anything which deviates from our reference design in terms of LO design unless you have the means to validate this yourself before you produce any boards. We do not have a spec defined for LO input to LO output isolation.

Regards,

Adrian

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AWR2243: 20GHz LO signal line (strip line) and GCPW Wilkinson power divider transform via structure