AWR1843BOOST: CCS Linker Error while building OOB demo with gtrack

Hi KP,

What all files are you using to build the final appimage?

BR,

Animesh Anand

I took the 3D_people_tracking_demo for reference , so whatever files the tracking demo is using.

Hi KP,

Can you kindly check in the makefile what all C files are included? So that I can verify the same.

BR,

Animesh Anand

can you tell me how can I update the .cfg and Pcount3D_res.h to work with XWR18XX

Not the radar config. The files like Pcount3D_mss.cfg, pcount3D_mss.h and r4f_linker.cmd.

I tried with the ones provided in mmwave_sdk. It gives me "Memory not sufficient" Error

Hi KP,

Can you share your linker cmd file? Let me look at ot once.

BR,

Animesh Anand

PCount3D_dss_linker.cmd

/*----------------------------------------------------------------------------*/
/* Linker Settings                                                            */
--retain="*(.intvecs)"

/*----------------------------------------------------------------------------*/
/* Include Libraries */
-llibdpm_xwr18xx.ae674
-llibmailbox_xwr18xx.ae674
-llibsoc_xwr18xx.ae674
-llibosal_xwr18xx.ae674
-ldsplib.ae674
//-opcount3D_dss_pe674.oe674
/* Section Configuration                                                      */
SECTIONS
{
    systemHeap : {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
    //.l3ram: {} >> L3SRAM
    .dpc_l1Heap  : { } > L1DSRAM
    .dpc_l2Heap: { } >> L2SRAM_UMAP0 | L2SRAM_UMAP1
	.ovly > L2SRAM_UMAP0 | L2SRAM_UMAP1
	
    /* L3SRAM has code that is overlaid with data, so data must be
       marked uninitialized. Application can initialize this section
       using _L3data_* symbols defined below. Code should be written carefully as
       these are linker symbols (see for example http://e2e.ti.com/support/development_tools/compiler/f/343/t/92002 ):
        
        extern far uint8_t _L3data_start; // the type here does not matter
        extern far uint8_t _L3data_size;  // the type here does not matter

        memset((void *)_symval(&_L3data_start), 0, (uint32_t) _symval(&_L3data_size));
    */ 
    .l3data: type=NOINIT, start(_L3data_start), size(_L3data_size), load=L3SRAM PAGE 1
	
    .fastCode:
    {
		RADARDEMO_detectionCFAR_priv.oe674 (.text:RADARDEMO_detectionCFAR_raCAAll)
		RADARDEMO_aoaEst2DCaponBF_heatmapEst.oe674 (.text:RADARDEMO_aoaEst2DCaponBF_raHeatmap)
		RADARDEMO_aoaEst2DCaponBF_rnEstInv.oe674 (.text:RADARDEMO_aoaEst2DCaponBF_covInv)
		MATRIX_cholesky.oe674 (.text:MATRIX_cholesky_flp_inv)
		RADARDEMO_aoaEst2DCaponBF_staticRemoval.oe674 (.text:RADARDEMO_aoaEst2DCaponBF_clutterRemoval)
		RADARDEMO_aoaEst2DCaponBF_bpmDecoding.oe674 (.text:RADARDEMO_aoaEst2DCaponBF_bpmDecoding)
		copyTranspose.oe674 (.text:copyTranspose)
		//dsplib.ae674<*.obj>(.text) 
    } load=L3SRAM PAGE 0 , run=L1PSRAM PAGE 0, table(_pcount3DDemo_fastCode_L1PSRAM_copy_table, compression=off)
	

    .hsramCode:
    {
		libdpm_xwr18xx.ae674 (.text:DPM_deinit)
		libmailbox_xwr18xx.ae674 (.text:Mailbox_close)
		libdpm_xwr18xx.ae674 (.text:DPM_pipeDeinit)
		dss_main.oe674 (.text:Pcount3DDemo_sensorStopEpilog)
		
		rts*.lib (.text:_outc)
		rts*.lib (.text:_outs)
		rts*.lib (.text:printf)
		rts*.lib (.text:_ltostr)
		rts*.lib (.text:__c6xabi_isnan)
		rts*.lib (.text:_ecpy)
		rts*.lib (.text:_mcpy)
		rts*.lib (.text:_pconv_g)
		rts*.lib (.text:fcvt)
		rts*.lib (.text:_pconv_f)
		rts*.lib (.text:_pconv_e)
		rts*.lib (.text:_pconv_a)
		rts*.lib (.text:__TI_printfi)
		rts*.lib (.text:fputs)
		rts*.lib (.text:fputc)
		rts*.lib (.text:__c6xabi_divul)
		rts*.lib (.text:__c6xabi_divd)
		rts*.lib (.text:frexp)
		rts*.lib (.text:ldexp)
		
    } load=L3SRAM PAGE 0, run=HSRAM PAGE 0, table(_pcount3DDemo_configCode_HSRAM_copy_table, compression=off)

    .overlaidCode:
    {
    	RADARDEMO_aoaEst2DCaponBF.oe674 (.text:RADARDEMO_aoaEst2DCaponBF_create)
    	RADARDEMO_detectionCFAR.oe674 (.text:RADARDEMO_detectionCFAR_create)
    	RADARDEMO_aoaEst2DCaponBF_utils.oe674 (.text:tw_gen_float)
    	radarProcess.oe674 (.text:DPU_radarProcess_init)
		objectdetection.oe674 (.text:DPC_ObjectDetection_deinit)
		radarOsal_malloc.oe674 (.text:radarOsal_memAlloc)
		radarOsal_malloc.oe674 (.text:radarOsal_memInit)
    	radarOsal_malloc.oe674 (.text:radarOsal_memDeInit)
		radarOsal_malloc.oe674 (.text:radarOsal_printHeapStats)
		objectdetection.oe674 (.text:DPC_ObjectDetection_init)
		RADARDEMO_aoaEst2DCaponBF_utils.oe674 (.text:cosdp_i)
		

    	RADARDEMO_aoaEst2DCaponBF_angleEst.oe674 (.text:RADARDEMO_aoaEst2DCaponBF_aeEstElevAzim)
		libedma_xwr18xx.ae674<*.oe674>(.text)
		dss_main.oe674 (.text:MmwDemo_edmaOpen)
		dss_main.oe674 (.text:MmwDemo_edmaInit)
		dss_main.oe674 (.text:MmwDemo_edmaBlockCopy)
		dss_main.oe674 (.text:MmwDemo_copyTable)
		cycle_measure.oe674 (.text:cache_setMar)
		dss_main.oe674 (.text:MmwDemo_EDMA_errorCallbackFxn)
		dss_main.oe674 (.text:MmwDemo_EDMA_transferControllerErrorCallbackFxn)
		
		libedma_xwr18xx.ae674 (.far:EDMA_object)

		dss_main.oe674 (.text:main)
		dss_main.oe674 (.text:Pcount3DDemo_dssInitTask)
    } load=L3SRAM PAGE 0 

    .unUsedCode:
    {
    	RADARDEMO_detectionCFAR_priv.oe674 (.text:RADARDEMO_detectionCFAR_CAAll)
    	RADARDEMO_detectionCFAR_priv.oe674 (.text:RADARDEMO_detectionCFAR_OS)
    } load=L3SRAM PAGE 0
	
    .slowCode:
    {
		libmailbox_xwr18xx.ae674 (.text:Mailbox_init)
		libdpm_xwr18xx.ae674 (.text:DPM_init)
		libmailbox_xwr18xx.ae674 (.text:Mailbox_open)
		libsoc_xwr18xx.ae674 (.text:SOC_deviceInit)
		libdpm_xwr18xx.ae674 (.text:DPM_mboxInit)
		libosal_xwr18xx.ae674 (.text:SemaphoreP_create)
		libdpm_xwr18xx.ae674 (.text:DPM_pipeInit)
		libsoc_xwr18xx.ae674 (.text:SOC_init)

		objectdetection.oe674 (.text:DPC_ObjDetDSP_preStartConfig)
		
		//pcount3D_dss_pe674.oe674 (.text:xdc_runtime_System_printfExtend__I)
		
		//rts*.lib (.text:__TI_tls_init) //not copied to HSRAM, but moved to L3
		rts*.lib (.text:__c6xabi_divf) 
		rts*.lib (.text:setvbuf)
		rts*.lib (.text:HOSTrename)
		rts*.lib (.text:getdevice)
		rts*.lib (.text:__TI_closefile) 
		rts*.lib (.text:atoi)
		rts*.lib (.text:fflush)
		rts*.lib (.text:fseek)  
		rts*.lib (.text:HOSTlseek)
		rts*.lib (.text:HOSTopen)
		rts*.lib (.text:HOSTwrite)
		rts*.lib (.text:__TI_ltoa)  
		rts*.lib (.text:__TI_wrt_ok)
		rts*.lib (.text:close)
		rts*.lib (.text:HOSTread)
		rts*.lib (.text:HOSTunlink)  
		rts*.lib (.text:__TI_doflush)
		rts*.lib (.text:__divu)
		rts*.lib (.text:modf)
		rts*.lib (.text:HOSTclose)  

		rts*.lib (.text:__TI_cleanup)
		rts*.lib (.text:__c6xabi_fixfu)
		rts*.lib (.text:__remu)
		rts*.lib (.text:finddevice)
		rts*.lib (.text:__TI_readmsg)
		rts*.lib (.text:__c6xabi_fixdu)
		rts*.lib (.text:__c6xabi_llshl)
		rts*.lib (.text:unlink)
		rts*.lib (.text:__TI_writemsg)
		rts*.lib (.text:__c6xabi_llshru)
		rts*.lib (.text:_subcull)
		rts*.lib (.text:lseek)
		rts*.lib (.text:write)
		rts*.lib (.text:__TI_frcmpyd_div)
		rts*.lib (.text:__c6xabi_isinf)
		rts*.lib (.text:wcslen)
    } load=L3SRAM PAGE 0 (HIGH)
	
}
/*----------------------------------------------------------------------------*/

/*----------------------------------------------------------------------------*/
/* r4f_linker.cmd                                                                 */
/*                                                                            */
/* (c) Texas Instruments 2016, All rights reserved.                           */
/*                                                                            */

/* USER CODE BEGIN (0) */
/* USER CODE END */


/*----------------------------------------------------------------------------*/
/* Linker Settings                                                            */
--retain="*(.intvecs)"

/*----------------------------------------------------------------------------*/
/* Memory Map                                                                 */
#define MMWAVE_L3RAM_SIZE (MMWAVE_L3RAM_NUM_BANK*MMWAVE_SHMEM_BANK_SIZE - MMWAVE_MSSUSED_L3RAM_SIZE)
MEMORY{
PAGE 0:
    VECTORS  (X)  : origin=0x00000000 length=0x00000100
    PROG_RAM (RX) : origin=0x00000100 length=0x0007FF00+(MMWAVE_SHMEM_TCMA_NUM_BANK*MMWAVE_SHMEM_BANK_SIZE)
    DATA_RAM (RW) : origin=0x08000000 length=0x00030000+(MMWAVE_SHMEM_TCMB_NUM_BANK*MMWAVE_SHMEM_BANK_SIZE)
    L3_RAM (RW)   : origin=0x51000000 length=0x00000000+(MMWAVE_MSSUSED_L3RAM_SIZE)
    HWA_RAM (RW)  : origin=0x52030000 length=0x00010000
    HS_RAM (RW)   : origin=0x52080000 length=0x8000
PAGE 1:
    L3_RAM (RW)   : origin=0x51000000 length=0x00000000+(MMWAVE_MSSUSED_L3RAM_SIZE)
}

/*----------------------------------------------------------------------------*/
/* Section Configuration                                                      */
SECTIONS{
    .intvecs : {} > VECTORS
    .text    : {} > PROG_RAM
    .const   : {} > PROG_RAM
    .cinit   : {} > PROG_RAM
    .pinit   : {} > PROG_RAM
    .bss     : {} > DATA_RAM
    .data    : {} > DATA_RAM
    .stack   : {} > DATA_RAM
}
/*----------------------------------------------------------------------------*/

/*
 * Copyright (c) 2016, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
Original:
#define L1P_CACHE_SIZE (32*1024)
#define L1D_CACHE_SIZE (32*1024)
*/
#define L1P_CACHE_SIZE (4*1024)
#define L1D_CACHE_SIZE (16*1024)
#define MMWAVE_L3RAM_SIZE (MMWAVE_L3RAM_NUM_BANK*MMWAVE_SHMEM_BANK_SIZE)

MEMORY
{
PAGE 0:

#if (L1P_CACHE_SIZE < 0x8000)
    L1PSRAM:        o = 0x00E00000, l = (0x00008000 - L1P_CACHE_SIZE)
#endif
#if (L1D_CACHE_SIZE < 0x8000)
    L1DSRAM:        o = 0x00F00000, l = (0x00008000 - L1D_CACHE_SIZE)
#endif
    L2SRAM_UMAP1:   o = 0x007E0000, l = 0x00020000
    L2SRAM_UMAP0:   o = 0x00800000, l = 0x00020000
    L3SRAM:         o = 0x20000000, l = MMWAVE_L3RAM_SIZE
    HWA_RAM :       o = 0x21030000, l = 0x00010000
    HSRAM:          o = 0x21080000, l = 0x8000

    /* PAGEs 1 and onwards are for overlay purposes for memory optimization.
       Some examples:
       1. Overlay one-time only text with uninitialized data.
       2. Overlay L1PSRAM data path processing fast code and use copy tables
          to page in (before entering data path) and out of L1PSRAM (when entering
          sleep/low power).
    */
PAGE 1:
    L3SRAM:         o = 0x20000000, l = MMWAVE_L3RAM_SIZE
}

/* Set L1D, L1P and L2 Cache Sizes */
ti_sysbios_family_c64p_Cache_l1dSize = L1D_CACHE_SIZE;
ti_sysbios_family_c64p_Cache_l1pSize = L1P_CACHE_SIZE;
ti_sysbios_family_c64p_Cache_l2Size  = 0;

SECTIONS
{
    /* hard addresses forces vecs to be allocated there */
    .vecs:  {. = align(32); } > 0x007E0000

    /* Allocate data preferentially in one UMAP and code (.text) in another,
       this can improve performance due to simultaneous misses from L1P
       and L1D caches to L2 SRAM, for more information see C674 Megamodule
       User Guide section "Level 2 Memory Architecture".
       The linker notation "X >> Y | Z" indicates section X is first allocated in Y
       and allowed to overflow into Z and can be split from Y to Z.
       The linker notation "X > Y | Z" indicates section X is first allocated in Y
       and allowed to overflow into Z and cannot be split from Y to Z. Some sections
       like bss are not allowed to be split so > notation is used for them */

    .fardata:  {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
    .const:    {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
    .switch:   {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
    .cio:      {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
    .data:     {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1

    .rodata:   {} > L2SRAM_UMAP0 | L2SRAM_UMAP1
    .bss:      {} > L2SRAM_UMAP0 | L2SRAM_UMAP1
    .neardata: {} > L2SRAM_UMAP0 | L2SRAM_UMAP1
    .stack:    {} > L2SRAM_UMAP0 | L2SRAM_UMAP1
    .cinit:    {} > L2SRAM_UMAP0 | L2SRAM_UMAP1
    .far:      {} > L2SRAM_UMAP0 | L2SRAM_UMAP1

    .text: {} >> L2SRAM_UMAP1 | L2SRAM_UMAP0
}

Memory error went away when I changed 

Hi KP,

How are you running the application on the device? Are you individually running appimages in each core?

BR,

Animesh Anand

I tried both ways, directly flashing binary using the uniflash, CLI never responds with this method.
Then I tried debugging it, for which I flashed individual images, xe674, and xer4f. With this methods, I tried printing some debug messages on every steps and found that the code never goes beyond DPM_synch followed by a red light 

Hi KP,

Can you further debug in which function you are getting the issue? Just step inside those function.

BR,

Animesh Anand

The function DPM_synch is where the code gets stuck.

Hi KP.

Are you able to run the original demo that is present in SDK?

BR,

Animesh Anand

Yes I am able to run the original OOB demo

When you load the individual binary on the core. Just halt the core when you get stuck. And see where exactly you are stuck in each core.

BR,

Animesh Anand