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TMP100: Questions about TMP100 interface.

Kazuya Nakai59
Guru 21595 points
Part Number: TMP100

Tool/software:

Hello guys,

One of my customers is considering using TMP100 for their next products.

At this moment, they have the following questions.
Could you please give me your reply?

Q1.
Can the TMP100 be software reset with a General Call or any other way?

Q2.
They think TMP100 may occupy I2C bus if the TMP100 freezes due to noise in data output mode of I2C bus
If the situation is happened, is there any method to release the bus?
For example, if a dummy clock (9 clocks) is sent from the master side, can the bus be released from TMP100 which was frozen due to noise?

Your reply would be much appreciated.

Best regards,
Kazuya Nakai.

  • 0
    TI__Expert 7170 points

    Hi Nakai,

    Thank you for reaching out. Please see my feedback below:

    • Yes, the device latches the address pins and resets with a general call reset command --> 0x06
    • The controller can issue a forced stop condition to stop communication with the device which makes the device release the bus. Vih spec is a minimum of 70% of V+. Keep in mind that this is an open-drain interface so any noise on the bus will potentially come from either GND, supply, or long traces/coupling which can be mitigated using passive components

    Please let me know if there are any other questions about this device.

    Best regards,

    Simon Rojas

  • 0 in reply to Simon Rojas Avila
    Guru 21595 points

    Hi Simon,

    Thank you very much for your reply.

    Could I ask you a few additional questions as the below?

    Q1.
    Is there any way to execute TMP100 software rest except the general call sending? 

    Q2.
    Is the software reset not executed by dummy clock (9 clocks or so on) sending?
    The customer says that there are some EEPROM which can be executed by the dummy clock sending.

    Q3. 
    Please let me ask again.
    If the TMP100 freezes with SDA low level due to noise etc,
    is there any way to release the bus from L level?
    if a dummy clock (9 clocks so on) is sent from the master side, is the bus released?

    Thank you again and best regards,
    Kazuya.

  • 0 in reply to Kazuya Nakai59
    TI__Expert 7170 points

    Hi Kazuya,

    Please see my responses below:

    • The device can only reset with general call reset (SW reset) or power cycling
    • SW reset is issued by sending a 0x06 command over the SDA line after issuing a START condition with the clock running. This device does not have any EEPROM
    • If the SDA line is stuck from the device, the master can send 9 clock counts to release SDA

    Best regards,

    Simon Rojas

  • 0 in reply to Simon Rojas Avila
    Guru 21595 points

    Hi Simon,

    Thank you very much for your reply.

    Could I ask you an additional question as the below?

    >If the SDA line is stuck from the device, the master can send 9 clock counts to release SDA.

    Is there explanation of this function in the device datasheet?

    Thank you again and best regards,
    Kazuya. 

  • 0 in reply to Kazuya Nakai59
    TI__Expert 7170 points

    Hi Kazuya,

    This is not explained in the datasheet but it's derived from the I2C communication standard since the device will read the 9 clock pulses (1 byte + ACK) and release SDA. Keep in mind that this is not a failure mode that we have seen with this device. As long as the device is receiving clock pulses, it would only keep the line low if it is trying to send all 0s on SDA.

    Best regards,

    Simon Rojas

  • 0 in reply to Simon Rojas Avila
    Guru 21595 points

    Hi Simon,

    Thank you very much for your reply.

    Could I ask you a similar question?

    Q.
    Do you have any document which explains TMP100 has this function except the datasheet?

    Thank you and best regards,
    Kazuya.

  • 0 in reply to Kazuya Nakai59
    TI__Expert 7170 points

    Hi Kazuya,

    We do not have such document at this point. This is derived from the I2C standard rather than a specific feature of the device.

    Best regards,

    Simon Rojas