Tool/software:
Hi, there some problem when debug with LP877451Q1,
There is a pmic_write_test code to test pmic, but it is implemented with IIC,
I modified it to communicate with LP877451Q1 with mibspi controller.
The setting is:
and the result protocol is:
the implementaion code is:
pmic_read_write.c
/*
* Copyright (C) 2023 Texas Instruments Incorporated
*
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* modification, are permitted provided that the following conditions
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*
* Redistributions of source code must retain the above copyright
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*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
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*
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* its contributors may be used to endorse or promote products derived
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*
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*/
/**
* @file pmic_read_write.c
*
* @brief
* PMIC Read and Write example code
*/
/** @mainpage PMIC Read and Write Application for awr294x
*
* ### Introduction
* The Power Management IC (LP8772x-Q1) is designed to meet the power management requirements of the radar device.
* It has three buck converters, one linear regulator and one load switch. The PMIC device is controlled by SPI interface.
*
* This example is a generic application which can be used to program the PMIC.
* It has three cases which is selected based on user input.
* - Read all registers: Reads and prints all 99 PMIC register contents on UART interface
* - Write to a register: Writes to user provided register address and reads back register content to verify written value.
* - Read a register: Read and print user provided register address on UART interface
*
* ### Procedure:
* Connect to application port on any serial terminal. Run pmic_read_write application on MSS core.
* The following statements are printed on the terminal and it waits for the user input.
*
* @image html input.png "Serial Terminal"
*
*
* ### Sample Output
*
* @code
*
* [PMIC] device found at address 0x60
* [PMIC] Select Test type:
* 0: Read all registers
* 1: Write to register
* 2: Read register
* 0
* [PMIC] RegName = DEV_REV, Address = 0x1, RegVal = 0x96
* [PMIC] RegName = NVM_CODE_1, Address = 0x2, RegVal = 0x1
* [PMIC] RegName = NVM_CODE_2, Address = 0x3, RegVal = 0x0
* [PMIC] RegName = MANUFACTURING_VER, Address = 0x4, RegVal = 0x0
* [PMIC] RegName = FSM_COMMAND_REG, Address = 0x5, RegVal = 0x0
* [PMIC] RegName = BLOCK_EN_CTRL, Address = 0x6, RegVal = 0x7F
* [PMIC] RegName = RECOV_CNT_CONTROL, Address = 0x7, RegVal = 0x0
* [PMIC] RegName = ESM_START_REG, Address = 0x8, RegVal = 0x0
* [PMIC] RegName = REGISTER_LOCK, Address = 0x9, RegVal = 0x1
* [PMIC] RegName = SCRATCH_PAD_REG_1, Address = 0xA, RegVal = 0x0
* [PMIC] RegName = SCRATCH_PAD_REG_2, Address = 0xB, RegVal = 0x0
* [PMIC] RegName = SCRATCH_PAD_REG_3, Address = 0xC, RegVal = 0x0
* [PMIC] RegName = SCRATCH_PAD_REG_4, Address = 0xD, RegVal = 0x0
* [PMIC] RegName = WD_ANSWER_REG, Address = 0xE, RegVal = 0x0
* [PMIC] RegName = WD_ENABLE_REG, Address = 0xF, RegVal = 0x3
* [PMIC] RegName = WD_MODE_REG, Address = 0x10, RegVal = 0x4
* [PMIC] RegName = BUCK1_VOUT, Address = 0x11, RegVal = 0x2D
* [PMIC] RegName = BUCK2_VOUT, Address = 0x12, RegVal = 0x5
* [PMIC] RegName = BUCK3_VOUT, Address = 0x13, RegVal = 0xF
* [PMIC] RegName = LDO_LS1_VMON1_PG_LEVEL, Address = 0x14, RegVal = 0x10
* [PMIC] RegName = LS2_VMON2_PG_LEVEL, Address = 0x15, RegVal = 0x70
* [PMIC] RegName = BUCK1_MON_CONF, Address = 0x16, RegVal = 0x70
* [PMIC] RegName = BUCK2_MON_CONF, Address = 0x17, RegVal = 0x57
* [PMIC] RegName = BUCK3_MON_CONF, Address = 0x18, RegVal = 0x57
* [PMIC] RegName = LDO_LS1_VMON1_MON_CONF, Address = 0x19, RegVal = 0x57
* [PMIC] RegName = LS2_VMON2_MON_CONF, Address = 0x1A, RegVal = 0xF4
* [PMIC] RegName = CLK_CONF, Address = 0x1B, RegVal = 0xA4
* [PMIC] RegName = INTERFACE_CONF, Address = 0x1C, RegVal = 0x85
* [PMIC] RegName = FUNC_CONF, Address = 0x1D, RegVal = 0x2D
* [PMIC] RegName = VCCA_MON_CONF, Address = 0x1E, RegVal = 0x40
* [PMIC] RegName = BUCK_LDO_LS1_VMON1_DEGLIT, Address = 0x1F, RegVal = 0xFB
* [PMIC] RegName = BUCK1_SEQUENCE, Address = 0x20, RegVal = 0xE8
* [PMIC] RegName = BUCK2_SEQUENCE, Address = 0x21, RegVal = 0x0
* [PMIC] RegName = BUCK3_SEQUENCE, Address = 0x22, RegVal = 0x3
* [PMIC] RegName = LDO_LS1_VMON1_SEQUENCE, Address = 0x23, RegVal = 0x2
* [PMIC] RegName = LS2_VMON2_SEQUENCE, Address = 0x24, RegVal = 0x4
* [PMIC] RegName = GPO_SEQUENCE, Address = 0x25, RegVal = 0x1
* [PMIC] RegName = NRSTOUT_SEQUENCE, Address = 0x26, RegVal = 0x0
* [PMIC] RegName = REG_OV_CONF, Address = 0x27, RegVal = 0x9
* [PMIC] RegName = REG_UV_CONF, Address = 0x28, RegVal = 0xEE
* [PMIC] RegName = REG_SC_CONF, Address = 0x29, RegVal = 0x1D
* [PMIC] RegName = VCCA_LS2_VMON2_OV_CONF, Address = 0x2A, RegVal = 0xEA
* [PMIC] RegName = VCCA_LS2_VMON2_UV_CONF, Address = 0x2B, RegVal = 0xA0
* [PMIC] RegName = MASK_BUCK1_2, Address = 0x2C, RegVal = 0xA0
* [PMIC] RegName = MASK_BUCK3_LDO_LS1_VMON1, Address = 0x2D, RegVal = 0x44
* [PMIC] RegName = MASK_LS2_VMON2, Address = 0x2E, RegVal = 0x44
* [PMIC] RegName = MASK_VCCA, Address = 0x2F, RegVal = 0x4
* [PMIC] RegName = MASK_STARTUP, Address = 0x30, RegVal = 0x0
* [PMIC] RegName = MASK_MISC, Address = 0x31, RegVal = 0x0
* [PMIC] RegName = MASK_MODERATE_ERR, Address = 0x32, RegVal = 0xC0
* [PMIC] RegName = MASK_COMM_ERR, Address = 0x33, RegVal = 0x0
* [PMIC] RegName = MASK_ESM, Address = 0x34, RegVal = 0x0
* [PMIC] RegName = CONFIG_1, Address = 0x35, RegVal = 0x0
* [PMIC] RegName = RECOV_CNT_REG_2, Address = 0x36, RegVal = 0x27
* [PMIC] RegName = ESM_DELAY1_REG, Address = 0x37, RegVal = 0xFF
* [PMIC] RegName = ESM_DELAY2_REG, Address = 0x38, RegVal = 0x0
* [PMIC] RegName = ESM_MODE_CFG, Address = 0x39, RegVal = 0x0
* [PMIC] RegName = ESM_HMAX_REG, Address = 0x3A, RegVal = 0x0
* [PMIC] RegName = ESM_HMIN_REG, Address = 0x3B, RegVal = 0x0
* [PMIC] RegName = ESM_LMAX_REG, Address = 0x3C, RegVal = 0x0
* [PMIC] RegName = ESM_LMIN_REG, Address = 0x3D, RegVal = 0x0
* [PMIC] RegName = WD_WIN1_CFG, Address = 0x3E, RegVal = 0x0
* [PMIC] RegName = WD_WIN2_CFG, Address = 0x3F, RegVal = 0x7F
* [PMIC] RegName = WD_LONGWIN_CFG, Address = 0x40, RegVal = 0x7F
* [PMIC] RegName = WD_QA_CFG, Address = 0x41, RegVal = 0xFF
* [PMIC] RegName = WD_THR_CFG, Address = 0x42, RegVal = 0xA
* [PMIC] RegName = SPREAD_SPECTRUM_CONFIG_1, Address = 0x43, RegVal = 0x3F
* [PMIC] RegName = SPREAD_SPECTRUM_CONFIG_2, Address = 0x43, RegVal = 0x3F
* [PMIC] RegName = CONFIG_CRC_REG_1, Address = 0x45, RegVal = 0x0
* [PMIC] RegName = CONFIG_CRC_REG_2, Address = 0x46, RegVal = 0x99
* [PMIC] RegName = INT_TOP, Address = 0x47, RegVal = 0x8
* [PMIC] RegName = INT_BUCK_LS2_VMON2, Address = 0x48, RegVal = 0x0
* [PMIC] RegName = INT_BUCK1_2, Address = 0x49, RegVal = 0x10
* [PMIC] RegName = INT_BUCK3_LDO_LS1_VMON1, Address = 0x4A, RegVal = 0x0
* [PMIC] RegName = INT_LS2_VMON2, Address = 0x4B, RegVal = 0x0
* [PMIC] RegName = INT_VCCA, Address = 0x4C, RegVal = 0x2
* [PMIC] RegName = INT_STARTUP, Address = 0x4D, RegVal = 0x4
* [PMIC] RegName = INT_MISC, Address = 0x4E, RegVal = 0x0
* [PMIC] RegName = INT_MODERATE_ERR, Address = 0x4F, RegVal = 0x0
* [PMIC] RegName = INT_SEVERE_ERR, Address = 0x50, RegVal = 0x18
* [PMIC] RegName = INT_FSM_ERR, Address = 0x51, RegVal = 0x0
* [PMIC] RegName = INT_COMM_ERR, Address = 0x52, RegVal = 0x0
* [PMIC] RegName = INT_ESM, Address = 0x53, RegVal = 0x44
* [PMIC] RegName = STAT_BUCK1_2, Address = 0x54, RegVal = 0x44
* [PMIC] RegName = STAT_BUCK3_LDO_LS1_VMON1, Address = 0x55, RegVal = 0x4
* [PMIC] RegName = STAT_LS2_VMON2, Address = 0x56, RegVal = 0x0
* [PMIC] RegName = STAT_VCCA, Address = 0x57, RegVal = 0xF6
* [PMIC] RegName = STAT_STARTUP, Address = 0x58, RegVal = 0x40
* [PMIC] RegName = STAT_MISC, Address = 0x59, RegVal = 0x2
* [PMIC] RegName = STAT_MODERATE_ERR, Address = 0x5A, RegVal = 0x0
* [PMIC] RegName = STAT_SEVERE_ERR, Address = 0x5B, RegVal = 0x0
* [PMIC] RegName = RECOV_CNT_REG_1, Address = 0x5C, RegVal = 0x0
* [PMIC] RegName = ESM_ERR_CNT_REG, Address = 0x5D, RegVal = 0xBC
* [PMIC] RegName = WD_QUESTION_ANSW_CNT, Address = 0x5E, RegVal = 0x0
* [PMIC] RegName = WD_ERR_STATUS, Address = 0x5F, RegVal = 0x0
* [PMIC] RegName = WD_FAIL_CNT_REG, Address = 0x60, RegVal = 0x1
* [PMIC] RegName = CONFIG_CRC_CONFIG, Address = 0x61, RegVal = 0x0
* [PMIC] RegName = CALCUL_CONFIG_CRC_1, Address = 0x62, RegVal = 0x0
* [PMIC] RegName = CALCUL_CONFIG_CRC_2, Address = 0x63, RegVal = 0x7F
*
* [PMIC] Select Test type:
* 0: Read all registers
* 1: Write to register
* 2: Read register
* 1
* Register Address (Valid Range: 0x01...0x63): 0x11
* Value to be written : 0x2E
*
* [PMIC] Select Test type:
* 0: Read all registers
* 1: Write to register
* 2: Read register
* 2
* Register Address (Valid Range: 0x01...0x63): 0x11
* Value at PMIC Register(0x11) : 0x2e
*
* [PMIC] Select Test type:
* 0: Read all registers
* 1: Write to register
* 2: Read register
* @endcode
*
*
*
*/
/* ============================================================================
*/
/**
@}
*/
/* ========================================================================== */
/* Include Files */
/* ========================================================================== */
/* Standard Include Files. */
#include <string.h>
#include <stdio.h>
#include <stdlib.h>
/* MCU+SDK Include Files: */
#include <ti/utils/test/pmic_read_write/awr294x/mssgenerated/ti_drivers_config.h>
#include <ti/utils/test/pmic_read_write/awr294x/mssgenerated/ti_board_config.h>
#include <ti/utils/test/pmic_read_write/awr294x/mssgenerated/ti_drivers_open_close.h>
#include <ti/utils/test/pmic_read_write/awr294x/mssgenerated/ti_board_open_close.h>
#include "FreeRTOS.h"
#include "task.h"
#include <drivers/mibspi.h>
#include "pmic_crc.h"
/* ========================================================================== */
/* Macros & Typedefs */
/* ========================================================================== */
/* FreeRTOS Task declarations. */
#define APP_TASK_PRI (5U)
#define APP_TASK_STACK_SIZE (2*1024U)
#define MAX_REG_ADDR (0x63U)
typedef struct {
const char* regName;
uint32_t address;
} PMIC_reg;
const PMIC_reg PMIC_regData[99] =
{
{"DEV_REV", 0x01},
{"NVM_CODE_1", 0x02},
{"NVM_CODE_2", 0x03},
{"MANUFACTURING_VER", 0x04},
{"FSM_COMMAND_REG", 0x05},
{"BLOCK_EN_CTRL", 0x06},
{"RECOV_CNT_CONTROL", 0x07},
{"ESM_START_REG", 0x08},
{"REGISTER_LOCK", 0x09},
{"SCRATCH_PAD_REG_1", 0x0A},
{"SCRATCH_PAD_REG_2", 0x0B},
{"SCRATCH_PAD_REG_3", 0x0C},
{"SCRATCH_PAD_REG_4", 0x0D},
{"WD_ANSWER_REG", 0x0E},
{"WD_ENABLE_REG", 0x0F},
{"WD_MODE_REG", 0x10},
{"BUCK1_VOUT", 0x11},
{"BUCK2_VOUT", 0x12},
{"BUCK3_VOUT", 0x13},
{"LDO_LS1_VMON1_PG_LEVEL", 0x14},
{"LS2_VMON2_PG_LEVEL", 0x15},
{"BUCK1_MON_CONF", 0x16},
{"BUCK2_MON_CONF", 0x17},
{"BUCK3_MON_CONF", 0x18},
{"LDO_LS1_VMON1_MON_CONF", 0x19},
{"LS2_VMON2_MON_CONF", 0x1A},
{"CLK_CONF", 0x1B},
{"INTERFACE_CONF", 0x1C},
{"FUNC_CONF", 0x1D},
{"VCCA_MON_CONF", 0x1E},
{"BUCK_LDO_LS1_VMON1_DEGLIT", 0x1F},
{"BUCK1_SEQUENCE", 0x20},
{"BUCK2_SEQUENCE", 0x21},
{"BUCK3_SEQUENCE", 0x22},
{"LDO_LS1_VMON1_SEQUENCE", 0x23},
{"LS2_VMON2_SEQUENCE", 0x24},
{"GPO_SEQUENCE", 0x25},
{"NRSTOUT_SEQUENCE", 0x26},
{"REG_OV_CONF", 0x27},
{"REG_UV_CONF", 0x28},
{"REG_SC_CONF", 0x29},
{"VCCA_LS2_VMON2_OV_CONF", 0x2A},
{"VCCA_LS2_VMON2_UV_CONF", 0x2B},
{"MASK_BUCK1_2", 0x2C},
{"MASK_BUCK3_LDO_LS1_VMON1", 0x2D},
{"MASK_LS2_VMON2", 0x2E},
{"MASK_VCCA", 0x2F},
{"MASK_STARTUP", 0x30},
{"MASK_MISC", 0x31},
{"MASK_MODERATE_ERR", 0x32},
{"MASK_COMM_ERR", 0x33},
{"MASK_ESM", 0x34},
{"CONFIG_1", 0x35},
{"RECOV_CNT_REG_2", 0x36},
{"ESM_DELAY1_REG", 0x37},
{"ESM_DELAY2_REG", 0x38},
{"ESM_MODE_CFG", 0x39},
{"ESM_HMAX_REG", 0x3A},
{"ESM_HMIN_REG", 0x3B},
{"ESM_LMAX_REG", 0x3C},
{"ESM_LMIN_REG", 0x3D},
{"WD_WIN1_CFG", 0x3E},
{"WD_WIN2_CFG", 0x3F},
{"WD_LONGWIN_CFG", 0x40},
{"WD_QA_CFG", 0x41},
{"WD_THR_CFG", 0x42},
{"SPREAD_SPECTRUM_CONFIG_1", 0x43},
{"SPREAD_SPECTRUM_CONFIG_2", 0x43},
{"CONFIG_CRC_REG_1", 0x45},
{"CONFIG_CRC_REG_2", 0x46},
{"INT_TOP", 0x47},
{"INT_BUCK_LS2_VMON2", 0x48},
{"INT_BUCK1_2", 0x49},
{"INT_BUCK3_LDO_LS1_VMON1", 0x4A},
{"INT_LS2_VMON2", 0x4B},
{"INT_VCCA", 0x4C},
{"INT_STARTUP", 0x4D},
{"INT_MISC", 0x4E},
{"INT_MODERATE_ERR", 0x4F},
{"INT_SEVERE_ERR", 0x50},
{"INT_FSM_ERR", 0x51},
{"INT_COMM_ERR", 0x52},
{"INT_ESM", 0x53},
{"STAT_BUCK1_2", 0x54},
{"STAT_BUCK3_LDO_LS1_VMON1", 0x55},
{"STAT_LS2_VMON2", 0x56},
{"STAT_VCCA", 0x57},
{"STAT_STARTUP", 0x58},
{"STAT_MISC", 0x59},
{"STAT_MODERATE_ERR", 0x5A},
{"STAT_SEVERE_ERR", 0x5B},
{"RECOV_CNT_REG_1", 0x5C},
{"ESM_ERR_CNT_REG", 0x5D},
{"WD_QUESTION_ANSW_CNT", 0x5E},
{"WD_ERR_STATUS", 0x5F},
{"WD_FAIL_CNT_REG", 0x60},
{"CONFIG_CRC_CONFIG", 0x61},
{"CALCUL_CONFIG_CRC_1", 0x62},
{"CALCUL_CONFIG_CRC_2", 0x63},
};
/* ========================================================================== */
/* Function Declarations */
/* ========================================================================== */
static void PMIC_selectTestType(void);
static void PMIC_readAllRegs(void);
static void PMIC_writeTest(void);
static void PMIC_readTest(void);
static bool PMIC_write(uint8_t targetAddr, uint8_t *writeData, uint8_t *response);
static bool PMIC_read(uint8_t targetAddr, uint8_t *response);
/* ========================================================================== */
/* Structure Declarations */
/* ========================================================================== */
/* None */
/* ========================================================================== */
/* Global Variables */
/* ========================================================================== */
TaskHandle_t gAppTask;
StaticTask_t gAppTaskObj;
StackType_t gAppTskStackMain[APP_TASK_STACK_SIZE] __attribute__((aligned(32)));
/* ========================================================================== */
/* Function Definitions */
/* ========================================================================== */
#define SPI_CCRC_ENABLE 0
#define SPI_PCRC_ENABLE 0
#if SPI_CCRC_ENABLE
#define SPI_WR_CMD_LEN 4
#else
#define SPI_WR_CMD_LEN 3
#endif
#define SPI_WR_RESP_LEN 3
#define SPI_RD_CMD_LEN 3
#if SPI_PCRC_ENABLE
#define SPI_RD_RESP_LEN 4
#else
#define SPI_RD_RESP_LEN 3
#endif
#define SPI_READ 0x01
#define SPI_WRITE 0x00
static bool PMIC_write(uint8_t targetAddr, uint8_t *writeData, uint8_t *response)
{
int32_t retVal;
MIBSPI_Transaction spiTransaction;
uint8_t TxBuffer[SPI_WR_CMD_LEN];
uint8_t RespBuffer[SPI_WR_RESP_LEN];
memset(TxBuffer, 0U, SPI_WR_CMD_LEN);
memset(RespBuffer, 0U, SPI_WR_RESP_LEN);
/* Initiate transfer */
TxBuffer[0] = targetAddr;
TxBuffer[1] = 0<< 4; // bit4: (r:1 w:0)
TxBuffer[2] = writeData[0];
#if SPI_CCRC_ENABLE
spiTxBuffer[3] = crc8(&spiTxBuffer[0], SPI_WR_CMD_LEN - 1); // TBD
#endif
spiTransaction.count = SPI_WR_CMD_LEN;
spiTransaction.txBuf = (void *)TxBuffer;
spiTransaction.rxBuf = (void *)RespBuffer;
spiTransaction.peripheralIndex = 0U;
spiTransaction.arg = NULL;
retVal = MIBSPI_transfer(gMibspiHandle[CONFIG_MIBSPI0], &spiTransaction);
if((SystemP_SUCCESS != retVal) || (MIBSPI_TRANSFER_COMPLETED != spiTransaction.status))
DebugP_log("MIBSPI transfer failed!!\r\n");
else
memcpy(response, RespBuffer, SPI_WR_RESP_LEN);
return (retVal? false: true);
}
static bool PMIC_read(uint8_t targetAddr, uint8_t *response)
{
int32_t retVal;
MIBSPI_Transaction spiTransaction;
uint8_t TxBuffer[SPI_RD_CMD_LEN];
uint8_t RespBuffer[SPI_RD_RESP_LEN];
memset(TxBuffer, 0U, SPI_RD_CMD_LEN);
memset(RespBuffer, 0U, SPI_RD_RESP_LEN);
/* Initiate transfer */
TxBuffer[0] = targetAddr;
TxBuffer[1] = 1<< 4; // bit4: (r:1 w:0)
spiTransaction.count = SPI_RD_CMD_LEN;
spiTransaction.txBuf = (void *)TxBuffer;
spiTransaction.rxBuf = (void *)RespBuffer;
spiTransaction.peripheralIndex = 0U;
spiTransaction.arg = NULL;
retVal = MIBSPI_transfer(gMibspiHandle[CONFIG_MIBSPI0], &spiTransaction);
if((SystemP_SUCCESS != retVal) || (MIBSPI_TRANSFER_COMPLETED != spiTransaction.status))
DebugP_log("MIBSPI transfer failed!!\r\n");
else
memcpy(response, RespBuffer, SPI_RD_RESP_LEN);
return (retVal? false: true);
}
static void PMIC_selectTestType(void)
{
bool retry;
int32_t choice = -1;
do
{
DebugP_log("[PMIC] Select Test type:\r\n");
DebugP_log("\t0: Read all registers\r\n");
DebugP_log("\t1: Write to register\r\n");
DebugP_log("\t2: Read register\r\n\t");
// DebugP_scanf("%i", &choice);
choice = 0;
switch (choice)
{
case 0:
PMIC_readAllRegs();
retry = false;
break;
case 1:
PMIC_writeTest();
retry = false;
break;
case 2:
PMIC_readTest();
retry = false;
break;
default:
DebugP_log("\t[PMIC] Wrong option, try again...\r\n\n");
retry = true;
break;
}
}while (retry);
}
static void PMIC_readAllRegs(void)
{
uint8_t readAddr= 0;
uint8_t readBuffer[SPI_RD_RESP_LEN];
char * ptrRegName;
bool retVal = false;
for(uint8_t loopIndex = 0; (loopIndex < sizeof(PMIC_regData)/sizeof(PMIC_reg)); loopIndex++)
{
readAddr = PMIC_regData[loopIndex].address;
ptrRegName = (char *)PMIC_regData[loopIndex].regName;
retVal = PMIC_read(readAddr, &readBuffer[0]);
if (retVal)
DebugP_log("\t[PMIC] RegName = %s, Address = 0x%X, \t RegVal = 0x%X \r\n", ptrRegName, readAddr, readBuffer[2]);
else
DebugP_log("\t[PMIC] Read failed for RegName = %s, Address = 0x%X, \t RegVal = 0x%X \r\n", ptrRegName, readAddr, readBuffer[2]);
}
}
static void PMIC_writeTest(void)
{
uint8_t regAddr = 0;
uint8_t regVal = 0;
bool retVal = false;
uint8_t writeResp[SPI_WR_RESP_LEN];
DebugP_log("\tRegister Address (Valid Range: 0x01...0x63): \t");
DebugP_scanf("%i", ®Addr);
DebugP_log("\tValue to be written : \t");
DebugP_scanf("%i", ®Val);
if(regAddr > MAX_REG_ADDR)
DebugP_log("\tERROR: Invalid PMIC Address\r\n");
else
{
retVal = PMIC_write(regAddr, ®Val, &writeResp[0]);
if(retVal)
DebugP_log("Write success for RegAddr = 0x%X, RegVal = 0x%X\r\n", regAddr, regVal);
else
DebugP_log("Write failed for RegAddr = 0x%X, RegVal = 0x%X\r\n", regAddr, regVal);
}
return;
}
static void PMIC_readTest(void)
{
uint8_t readAddr = 0;
uint8_t readResp[SPI_RD_RESP_LEN];
bool retVal = false;
DebugP_log("\tRegister Address (Valid Range: 0x01...0x63): \t");
DebugP_scanf("%i", &readAddr);
/* Read PMIC register */
retVal = PMIC_read(readAddr , &readResp[0]);
if(retVal)
DebugP_log("\tValue at PMIC Register(0x%02x) : 0x%02x\t\r\n", readAddr, readResp[2]);
else
DebugP_log("\tRead failed for RegAddr = 0x%X\r\n", readAddr);
}
void Pmic_read_write_test(void* args)
{
Drivers_open();
Board_driversOpen();
// while(1)
{
PMIC_selectTestType();
DebugP_log("\r\n");
}
Board_driversClose();
Drivers_close();
vTaskDelete(NULL);
}
int main (void)
{
/* init SOC specific modules */
System_init();
Board_init();
/* This task is created at highest priority, it should create more tasks and then delete itself */
gAppTask = xTaskCreateStatic( Pmic_read_write_test,
"Pmic_read_write_test",
APP_TASK_STACK_SIZE,
NULL,
APP_TASK_PRI,
gAppTskStackMain,
&gAppTaskObj );
configASSERT(gAppTask != NULL);
/* Start the scheduler to start the tasks executing. */
vTaskStartScheduler();
/* The following line should never be reached because vTaskStartScheduler()
will only return if there was not enough FreeRTOS heap memory available to
create the Idle and (if configured) Timer tasks. Heap management, and
techniques for trapping heap exhaustion, are described in the book text. */
DebugP_assertNoLog(0);
}
How to configure mibspi to access LP877451Q1, are there some reference setting or drive code avaiable?
Thanks.
