IWR6243: Question about LP mode on CSI interface

Chris Meng

Part Number: IWR6243

Tool/software:

Hi,

There is below statement in IWR6432 datasheet. Would you pls help to double confirm that there is no LP mode during IWR6243 CSI output? Customer would like to simplify the FPGA (host) CSI IP design.

The HS to LP transition of the CLK does not actually take place since the CLK is always ON in HS mode

Thanks,

Chris

9 months ago

0 Sharan S S 9 months ago

TI__Expert 4180 points

Hi,

We are looking into your query. Please allow us a couple of days to respond.

Regards

0 Swarnendu Chattopadhyay 9 months ago

TI__Expert 3750 points

Hi Chris,

That is correct. There is no transition in the clock signal depending upon the HS-LP transitions. The clock is continuous. This is to make the receiver side clock generation easier.

Thanks,

Swarnendu

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IWR6243: Question about LP mode on CSI interface