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IWRL6432BOOST: Error: "The initial (idle) state of the CLK line does not match the settings" when obtaining raw ADC data through SPI from Logic Analyzer

Mestiyage Don Inuka Gunathilaka
Prodigy 10 points
Part Number: IWRL6432BOOST
Other Parts Discussed in Thread: IWRL6432

Tool/software:

Hi TI Experts,

I have been evaluating the IWRL6432 mm Wave sensor for one of our applications, I wanted to obtain raw ADC data from the sensor using SPI through a Salae Logic 8 Analyzer. I followed the instructions as provided by your guide in the following link SPI Data Capture Users Guide. My Logic Analyzer could obtain a max sample speed of 50MS/s, The settings for my logic analyzer for obtaining SPI data are shown in below figures. I'm getting binary data but in some areas of the MOSI waveform, it gives an error showing "The initial (idle) state of the CLK line does not match the setting" at several areas of the entire waveform, although data comes during rest of times, I'm uncertain of the reliability of the data.

  • I used the source code provided in the radar toolbox with path ti\radar_toolbox_2_20_00_05\source\ti\examples\Fundamentals\xWRL6432_Raw_Data_Over_SPI and made the changes by defining the macros SPI_DATA_STREAMING to 1 and SPI_DATA_STREAMING_MODE to 2 for logic analyzer.
  • I flashed the program to the radar using the visualizer tool.
  • I pasted the configuration in the path ti\radar_toolbox_2_20_00_05\source\ti\examples\Fundamentals\xWRL6432_Raw_Data_Over_SPI\chirp_configs\xwrl6432boost named MotionDetect_SPI_Data_Capture_LA.cfg to tera term after connecting to the XDS110 UART COM port.
  • I started capture in logic analyzer and issued sensorStart 0 0 0 0 command after sending all previous configurations to the iwrl6432.
  • I receive the waveforms as follows

Why this error shown in above image occurs?

  • Are these steps that I followed for obtaining SPI data correct or is there anything I'm missing here?
  • Is the cause for this issue due to the fact that 50MS/s sample speed of my logic analyzer too low for this if so, are there any solutions such as lowering the SPI bitrate as such?
  • Is this error occurring due to some other issue maybe configuration file or source code.

Your support in this is much appreciated.

Thanks

  • 0
    TI__Intellectual 1310 points

    Hi,

    The steps that you are following are correct. Could you check if the SPI connections are done properly and the corresponding channels are present in Logic Analyzer.

    In addition, 50 MS/s might be a bit low considering the SPI frequency. It's better if you could test the same with a higher sampling rate.

    Could you hover over the clock and tell me the out frequency as well?

    Regards

  • 0 in reply to Sharan S S
    Prodigy 10 points

    Hi Sharan,

    Thank you for assisting. SPI connections are all good, it seems the clock pulses are not consistent during transfer of 32-bit data packets, figures of the clock waveform are as follows,

    I can increase the sample speed of my Logic Analyzer to maximum of 100MS/s only if I turn one of the channels off (for example MISO). I tried that as well images are below.

    If the reason for this problem is the low sampling speed, is there a possible way to solve this by some changes to SPI settings in code without effecting the ADC data to adjust for 50MS/s sample speed of the logic analyzer. If not, could I obtain the 1d-fft or 2d-fft data with reduced SPI bitrate to adjust for the same sample speed 50MS/s.

    Thank you.

  • 0 in reply to Sharan S S
    Prodigy 10 points

    Hi,

    The clock frequency is about 25MHz. The logic analyzer connections are properly established, I think the issue is with sampling speed of the Logic Analyzer, since when I lowered the bitrate of SPI to 15000000 from 25000000, the error disappeared, what are your thoughts on this, does lowering the bitrate has any effect on the ADC data received or will data be lost.

    Thank you.