Tool/software:
Hi all,
I’m designing a series of chirps that have a small bandwidth of about 10 MHz, but each subsequent chirp starts at the end frequency of the previous chirp. I’m hoping that this would lessen the time the PLL needs to settle and thus I could reduce the parameters for timing in between chirps to minimal values. However, when I’m programming the chirps onto the board I get an error that the idle time is less than the DFE settling time. For a sampling rate of 2.5 Msps, I haven’t been able to program an inter-chirp time of less than 6 us. Is there a way to bypass this error or is it a hard limit on those timing parameters?