AWR2944: Frame loss during CAN transmission

Hello aa,

Why can 2 CAN's not be used for this if you are using simultaneously?
Any specific reason for single CAN?

Regards,
Saswat Kumar

Each CAN channel has its designated purpose, and it is necessary to simultaneously transmit and receive a large amount of data on CAN1. Am I currently using the buffer mode, and do I need to switch to FIFO mode?

Hello a a,

Thanks for letting me know this information, I will reach out to my design team to check if there are any constraints in any mode and get back to you with this information.
Meanwhile I would suggest you test out the FIFO mode as well once and see if you are seeing any performance.

Regards,
Saswat Kumar

1. When using FIFO mode, the presence of a large amount of data on the bus can cause system anomalies, resulting in the Hwip entering an exception interrupt，stop in “vApplicationIRQHandlerConst ” interrupt handler.

2. I'd like to ask, are the CAN transmit FIFO and receive FIFO the same one? Currently, I'm using FIFO0 for receive filtering.

3. Additionally, Does the AWR2944 support DMA mode for CAN transmission? Are there any example programs provided?

How to set the transmit and receive interrupt priorities for CAN1? Must the interrupt callbacks for transmission and reception be the same function? In other words, if the MCAN1 interrupt is configured, are both the transmit and receive interrupts enabled by default?

/* Register interrupt */
HwiP_Params_init(&hwiPrms);
hwiPrms.intNum = APP_MCAN_INTR_NUM;
hwiPrms.callback = &App_mcanIntrISR;
status = HwiP_construct(&gMcanHwiObject, &hwiPrms);

To set up the CAN TX and RX FIFOs based on the mcan_external_loopback_interrupt example, can it be done solely by modifying the macros of APP_MCAN_TX_FIFO_CNT  and APP_MCAN_FIFO_0_CNT ? Are there any other changes that need to be synchronized?

/* Allocate Message RAM memory section to filter elements, buffers, FIFO */
/* Maximum STD Filter Element can be configured is 128 */
#define APP_MCAN_STD_ID_FILTER_CNT (1U)
/* Maximum EXT Filter Element can be configured is 64 */
#define APP_MCAN_EXT_ID_FILTER_CNT (0U)
/* Maximum TX Buffer + TX FIFO, combined can be configured is 32 */
#define APP_MCAN_TX_BUFF_CNT (0U)
#define APP_MCAN_TX_FIFO_CNT (32U)
/* Maximum TX Event FIFO can be configured is 32 */
#define APP_MCAN_TX_EVENT_FIFO_CNT (0U)
/* Maximum RX FIFO 0 can be configured is 64 */
#define APP_MCAN_FIFO_0_CNT (64U)
/* Maximum RX FIFO 1 can be configured is 64 and
* rest of the memory is allocated to RX buffer which is again of max size 64 */
#define APP_MCAN_FIFO_1_CNT (0U)

Hello a a,

You can search for FIFO in the code, there are a lot of places where you will find comments on where FIFO needs to be added and modified. Only the above will not be sufficient.
Also I think a mode of both buffer and FIFO is generally done

Regards,
Saswat Kumar

Here are specific examples of how to modify the send and receive FIFO sizes.

Additionally, how would you recommend using RX:FIFO and TX:buffer?

Thanks.

Hello a a,

I did not quite get from where this is picked up

a a said:

Here are specific examples of how to modify the send and receive FIFO sizes.

Along what lines you are looking for recommendation? We don't really have any recommendation and it depends on customer use case.
As it is a standard IP used, most of the customers already know what kind of configuration they are looking for.

Regards,
Saswat Kumar