TMP75: Consult about IIC bus timing

user4637774

Part Number: TMP75

Tool/software:

The chip communicates with the CPU through the IIC bus, and the bus transmission rate is 100Kbit/s. According to the requirements of the CPU data sheet, the maximum data output delay time(tI2OVKL) during write operations is 0.9us. However, based on our actual testing results, this time reaches 1.8us. Will this cause the CPU to fail to write to the chip?

6 months ago

+1 Simon Rojas Avila 6 months ago

TI__Expert 7170 points

Hi,

The TI2OVKL is a spec for data output from the device which is the max time that the device will hold the line low or leave it high after that bits respective clock.

In the example shown it seems you are showing a write operation to the device which does not relate to this spec. Assuming that you actually intend for that bit to be 0 (4th clock count) then there is not an issue in this communication shot.

Best regards,

Simon Rojas

0 user4637774 6 months ago in reply to Simon Rojas Avila

Intellectual 550 points

According to the data manual of tmp75, we did not see any AC timing requirements for the IIC bus standard mode. If we follow the IIC bus protocol in standard mode, our timing is met. Does tmp75 support the IIC bus in standard mode?

+1 Simon Rojas Avila 6 months ago in reply to user4637774

TI__Expert 7170 points

Yes, the device is characterized and follows the I2C standard mode according to spec.

Best regards,

Simon Rojas

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TMP75: Consult about IIC bus timing