Tool/software:
How to configure CSI2 lane to capture raw data? Is the captured data the same as the LVDS lane data?"
Thanks & Regards
Lei
Hi Lei,
I'm not sure from where you found that I am/was developer of cascade_radar_multi_datacollect. That is not true, although in past I might have supported 4xCascade queries in past as I was/am working for AWR device team.
Anyways, let me come back to the issue you raise here:
You mentioned that you are able to capture ADC data with mmWave Studio successfully but see some difference b/w studio vs cascade_radar_multi_datacollect.
Can you tell me what exactly difference you observe here? Ideally mmWave Studio is the tool to configure 4xCascade+MMWCAS-DSP-EVM and further capture ADC data to studio.
.
Regards,
Jitendra
Hi,Jitendra
Thank you for your reply.I saw the patch added to vision_sdk for AWR2243 support on the post , which is really cool, and it made me mistakenly think you were one of the developers working on it.
After three days of effort, we have resolved the data collection issue in TDMA mode, and the data collected using cascade_radar_multi_datacollect is now consistent with the data collected using the studio. However, we are encountering issues when collecting data in DDMA mode using cascade_radar_multi_datacollect. We are using radar_test_vector folder to configure the radar, which we've added parameters such as tx0PhaseShift, tx1PhaseShift, and tx2PhaseShift, along with modifications to txPhaseShifter. Below is the configuration file for the master rada,which it is not working as expected, and the size of the raw data we collect does not match the preset size.
# Any line that starts with a # is treated as a comment and ignored # Please do not start any non-blank line with a space # Please do not use hexa decimal values #srr-profile # NOTE: ADC Data NON-INTERLEAVED and 16-BIT version 4 ###### lvdsClkCfgArgs ###### # 0 - SDR Clock # 1 - DDR Clock (Only valid value for CSI2) laneClkCfg 1 # 0000b - 900 Mbps (DDR only) # 0001b - 600 Mbps (DDR only) # 0010b - 450 Mbps (SDR, DDR) # 0011b - 400 Mbps (DDR only) # 0100b - 300 Mbps (SDR, DDR) # 0101b - 225 Mbps (DDR only) # 0110b - 150 Mbps (SDR, DDR) dataRate 1 ###### hsiClkCfgArgs ###### # High Speed Interface Clock configurations # SDR - 0x5(900 mbps), 0xA(600 mbps), 0x6(450 mbps), # 0x2(400 mbps), 0xB(300 mbps), 0x7(225 mbps) # DDR - 0xD(900 mbps), 0x9(600 mbps), 0x5(450 mbps), # 0x1(400 mbps), 0xA(300 mbps), 0x6(225 mbps), # 0xB(150 mbps) hsiClk 10 # Total Number of chirp profile configurations # The profileCfgProfileId should be in the contiguous range [0..(numProfileCfg-1)] numProfileCfg 1 ###### BEGIN profileCfgArgs [0] ###### profileCfgProfileId 0 # Allowed values for "hpfCornerFreq1" # RL_RX_HPF1_175_KHz = 0 # RL_RX_HPF1_235_KHz = 1 # RL_RX_HPF1_350_KHz = 2 # RL_RX_HPF1_700_KHz = 3 hpfCornerFreq1 RL_RX_HPF1_175_KHz # Allowed values for "hpfCornerFreq2" # RL_RX_HPF2_350_KHz = 0 # RL_RX_HPF2_700_KHz = 1 # RL_RX_HPF2_1p4_MHz = 2 # RL_RX_HPF2_2p8_MHz = 3 # RL_RX_HPF2_5p0_MHz = 4 # RL_RX_HPF2_7p5_MHz = 5 # RL_RX_HPF2_10_MHz = 6 # RL_RX_HPF2_15_MHz = 7 hpfCornerFreq2 RL_RX_HPF2_350_KHz rxGain 30 digOutSampleRate 8000 numAdcSamples 256 adcStartTimeUSec 6 idleTimeUSec 5 rampEndTimeUSec 42 startFreqGhz 77 txOutPowerBackoffCode 0 txPhaseShifter 1 freqSlopeConstMhzPerUSec 79 txStartTimeUSec 0 ###### END profileCfgArgs [0] ###### # Transmit Antenna Mask # 1 - TX1 # 3 - TX1 + TX2 # 5 - TX1 + TX3 # 7 - TX1 + TX3 + TX2 txAntEnableMask 7 # Receive Antenna Mask rxAntEnableMask 15 # Total Number of chirp configurations # The chirpCfgArgsID should be in the contiguous range [0..(numChirpCfg-1)] # The pairs [chirpStartIdx, chirpEndIdx] across the profiles should be contiguous numChirpCfg 16 # Cascade - TX1, TX3 - AZIMUTH TX2 - ELEVATION ###### chirpCfgArgs ###### chirpCfgArgsID 0 chirpCfgProfileId 0 chirpStartIdx 0 chirpEndIdx 0 adcStartTimeVarUSec 0 idleTimeVarUSec 0 txEnable 7 startFreqVarHz 0 freqSlopeVarHz 0 tx0PhaseShift 0 tx1PhaseShift 0 tx2PhaseShift 0 ###### chirpCfgArgs ###### chirpCfgArgsID 1 chirpCfgProfileId 0 chirpStartIdx 1 chirpEndIdx 1 adcStartTimeVarUSec 0 idleTimeVarUSec 0 txEnable 7 startFreqVarHz 0 freqSlopeVarHz 0 tx0PhaseShift 20 tx1PhaseShift 24 tx2PhaseShift 28 ###### chirpCfgArgs ###### chirpCfgArgsID 2 chirpCfgProfileId 0 chirpStartIdx 2 chirpEndIdx 2 adcStartTimeVarUSec 0 idleTimeVarUSec 0 txEnable 7 startFreqVarHz 0 freqSlopeVarHz 0 tx0PhaseShift 40 tx1PhaseShift 48 tx2PhaseShift 56 ###### chirpCfgArgs ###### chirpCfgArgsID 3 chirpCfgProfileId 0 chirpStartIdx 3 chirpEndIdx 3 adcStartTimeVarUSec 0 idleTimeVarUSec 0 txEnable 7 startFreqVarHz 0 freqSlopeVarHz 0 tx0PhaseShift 60 tx1PhaseShift 8 tx2PhaseShift 20 ###### chirpCfgArgs ###### chirpCfgArgsID 4 chirpCfgProfileId 0 chirpStartIdx 4 chirpEndIdx 4 adcStartTimeVarUSec 0 idleTimeVarUSec 0 txEnable 7 startFreqVarHz 0 freqSlopeVarHz 0 tx0PhaseShift 16 tx1PhaseShift 32 tx2PhaseShift 48 ###### chirpCfgArgs ###### chirpCfgArgsID 5 chirpCfgProfileId 0 chirpStartIdx 5 chirpEndIdx 5 adcStartTimeVarUSec 0 idleTimeVarUSec 0 txEnable 7 startFreqVarHz 0 freqSlopeVarHz 0 tx0PhaseShift 36 tx1PhaseShift 56 tx2PhaseShift 12 ###### chirpCfgArgs ###### chirpCfgArgsID 6 chirpCfgProfileId 0 chirpStartIdx 6 chirpEndIdx 6 adcStartTimeVarUSec 0 idleTimeVarUSec 0 txEnable 7 startFreqVarHz 0 freqSlopeVarHz 0 tx0PhaseShift 56 tx1PhaseShift 16 tx2PhaseShift 40 ###### chirpCfgArgs ###### chirpCfgArgsID 7 chirpCfgProfileId 0 chirpStartIdx 7 chirpEndIdx 7 adcStartTimeVarUSec 0 idleTimeVarUSec 0 txEnable 7 startFreqVarHz 0 freqSlopeVarHz 0 tx0PhaseShift 12 tx1PhaseShift 40 tx2PhaseShift 4 ###### chirpCfgArgs ###### chirpCfgArgsID 8 chirpCfgProfileId 0 chirpStartIdx 8 chirpEndIdx 8 adcStartTimeVarUSec 0 idleTimeVarUSec 0 txEnable 7 startFreqVarHz 0 freqSlopeVarHz 0 tx0PhaseShift 32 tx1PhaseShift 0 tx2PhaseShift 32 ###### chirpCfgArgs ###### chirpCfgArgsID 9 chirpCfgProfileId 0 chirpStartIdx 9 chirpEndIdx 9 adcStartTimeVarUSec 0 idleTimeVarUSec 0 txEnable 7 startFreqVarHz 0 freqSlopeVarHz 0 tx0PhaseShift 52 tx1PhaseShift 24 tx2PhaseShift 60 ###### chirpCfgArgs ###### chirpCfgArgsID 10 chirpCfgProfileId 0 chirpStartIdx 10 chirpEndIdx 10 adcStartTimeVarUSec 0 idleTimeVarUSec 0 txEnable 7 startFreqVarHz 0 freqSlopeVarHz 0 tx0PhaseShift 8 tx1PhaseShift 48 tx2PhaseShift 24 ###### chirpCfgArgs ###### chirpCfgArgsID 11 chirpCfgProfileId 0 chirpStartIdx 11 chirpEndIdx 11 adcStartTimeVarUSec 0 idleTimeVarUSec 0 txEnable 7 startFreqVarHz 0 freqSlopeVarHz 0 tx0PhaseShift 28 tx1PhaseShift 8 tx2PhaseShift 52 ###### chirpCfgArgs ###### chirpCfgArgsID 12 chirpCfgProfileId 0 chirpStartIdx 12 chirpEndIdx 12 adcStartTimeVarUSec 0 idleTimeVarUSec 0 txEnable 7 startFreqVarHz 0 freqSlopeVarHz 0 tx0PhaseShift 48 tx1PhaseShift 32 tx2PhaseShift 16 ###### chirpCfgArgs ###### chirpCfgArgsID 13 chirpCfgProfileId 0 chirpStartIdx 13 chirpEndIdx 13 adcStartTimeVarUSec 0 idleTimeVarUSec 0 txEnable 7 startFreqVarHz 0 freqSlopeVarHz 0 tx0PhaseShift 4 tx1PhaseShift 56 tx2PhaseShift 44 ###### chirpCfgArgs ###### chirpCfgArgsID 14 chirpCfgProfileId 0 chirpStartIdx 14 chirpEndIdx 14 adcStartTimeVarUSec 0 idleTimeVarUSec 0 txEnable 7 startFreqVarHz 0 freqSlopeVarHz 0 tx0PhaseShift 24 tx1PhaseShift 16 tx2PhaseShift 8 ###### chirpCfgArgs ###### chirpCfgArgsID 15 chirpCfgProfileId 0 chirpStartIdx 15 chirpEndIdx 15 adcStartTimeVarUSec 0 idleTimeVarUSec 0 txEnable 7 startFreqVarHz 0 freqSlopeVarHz 0 tx0PhaseShift 44 tx1PhaseShift 40 tx2PhaseShift 36 ###### frameCfgArgs ###### frameChirpStartIdx 0 frameChirpEndIdx 11 # 0 means Infinite frames numFrames 0 # Number of Chirps per TX per frame numLoops 64 # Allowed values for "triggerSelect" # RL_FRAMESTRT_API_TRIGGER = 1, # RL_FRAMESTRT_SYNCIN_TRIGGER = 2 triggerSelect RL_FRAMESTRT_API_TRIGGER # Units of 5 nano-secs framePeriodicity 20000000 frameTriggerDelay 0 ###### dataPathCfgArgs ###### # b5:0 Packet 0 content selection\n # 000001 - ADC_DATA_ONLY # 000110 - CP_ADC_DATA # 001001 - ADC_CP_DATA # 110110 - CP_ADC_CQ_DATA # b7:6 Packet 0 virtual channel number (valid only for CSI2) # 00 Virtual channel number 0 (Default) # 01 Virtual channel number 1 # 02 Virtual channel number 2 # 03 Virtual channel number 3 transferFmtPkt0 1 # b5:0 Packet 0 content selection\n # 000000 - Suppress Packet 1 # 001110 - CP_CQ_DATA # 001011 - CQ_CP_DATA # b7:6 Packet 1 virtual channel number (valid only for CSI2) # 00 Virtual channel number 0 (Default) # 01 Virtual channel number # 02 Virtual channel number # 03 Virtual channel number transferFmtPkt1 0
I found that when cascade_radar_multi_datacollect starts and configures the radar using the following code,which it calls the Chains_ar12xxGetSampleCascadeConfig function in the file vision_sdk/apps/src/rtos/radar/src/common/chains_common_cascade_ar12xx_config_mimo.c for the initialization radar onfigurations. However, this file does not include the phase shift information required for DDMA mode. On the other hand, the file chains_common_cascade_ar12xx_config_bf.c at the same level contains more phase shift configurations. I would like to know if it is necessary to modify the configuration in chains_common_cascade_ar12xx_config_mimo.c for DDMA mode.
System_linkControl(SYSTEM_LINK_ID_APP_CTRL,
APP_CTRL_LINK_CMD_INIT_RADAR,
&pObj->radarConfigFiles,
sizeof(AppCtrl_RadarConfigFiles),
TRUE);
Thanks & Regards
Lei
Hi,
Yes, you are correct, the code provided in vision sdk does not support DDMA.
This code is old and the team that developed it, is no longer available for support.
Please make changes as you need. However our team does not have the knowledge to support it.
Thank you
Cesar