IWR6843ISK: Slave SPI transfers at high CLK frequencies (> 8MHz)

Adam Gild

Part Number: IWR6843ISK

Tool/software:

Hi there,

We are currently trying to up the CLK speed of our master controller, connected to an IWR6843ISK slave. It seems that up to 8MHz is working, however once we try 12.5MHz and 25MHz, the MISO line (data transmitted from the 6843) transmits incorrect bits.

I tested this by only transmitting patterns of 1010 1010 etc. See the results of my testing below:

8MHz:

12.5MHz:

25MHz:

As seen in the 12.5MHz and 25MHz captures, the 6843 seems to be struggling on the edges of its word length (which is 8 bits). This is observed very clearly in the 12.5MHz capture where every 1st bit is a 0 instead of a 1 (apart from the 1st bit of the entire transfer). In the 25MHz capture, for some reason, we only see it on the second word of the transfer.

Here is our SPI configuration:

Is there any assistance that could be offered regarding this behavior? Is there perhaps some hardware or software limitation to the SPI driver that will not allow it to operate at speeds faster than 8MHz?

Thanks,

Adam Gild

7 months ago

+1 Swarnendu Chattopadhyay 7 months ago

TI__Expert 3750 points

Hi Adam,

Please allow us a couple of days to respond.

Regards,

Swarnendu

0 Adam Gild 7 months ago

Prodigy 20 points

Also note, when the 6843 is supposed to be READing from the bus, it also pulls every 8th bit low:

We also discovered that the device is seemingly pulling that bit low, rather than inverting the bit (tested by setting the read tx dummy data to 0x0000 and observing no flipped bits).

0 Sharan S S 6 months ago in reply to Adam Gild

TI__Expert 4180 points

Hello,

Have you tried other SPI operating modes other than DMA? If so, are you experiencing a similar issue in that mode as well?

Regards,

Sharan

0 Adam Gild 6 months ago in reply to Sharan S S

Prodigy 20 points

Hi there,

I tried disabling DMA (which I believe makes it revert to polling), and I still see the same issue yes. Is there a requirement to toggle the CS for every word length (8 bits in this case)?

0 Sharan S S 6 months ago in reply to Adam Gild

TI__Expert 4180 points

Hi,

What is your input clk frequency with which SPI operates?

Regards,

Sharan

0 Adam Gild 6 months ago in reply to Sharan S S

Prodigy 20 points

It operates correctly at 8MHz. 12.5MHz and 25MHz it does not operate correctly. The logic captures are in the original post for all 3 of those frequencies

Thanks,

Adam

0 Sharan S S 6 months ago in reply to Adam Gild

TI__Expert 4180 points

Hi,

Please allow me a couple of days to check this internally and get back to you.

Regards

0 Adam Gild 6 months ago in reply to Sharan S S

Prodigy 20 points

Hey Sharan,

We have resolved this issue by using a 50nS delay between each word on the master processor. However, we are now hitting an issue of needing a delay between each 64 bytes of a transfer. I believe that this is a known issue on the 6843 SPI driver, but I was wondering if you had any more information on this issue, or if there are any known fixes for it that we could implement in the SDK?

I found a post detailing a similar issue:
e2e.ti.com/.../iwr6843-speed-up-larger-spi-transfers

0 Sharan S S 6 months ago in reply to Adam Gild

TI__Expert 4180 points

Hi,

Please take a look at the SPI driver documentation present in the SDK(mmwave_sdk_03_06_02_00-LTS\docs\mmwave_sdk_module_documentation)

to understand more about SPI transfer with multiple RAM buffer.

Regards,

Sharan

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IWR6843ISK: Slave SPI transfers at high CLK frequencies (> 8MHz)