IWR6843: HW triggerd mode, SYNC_IN periodicity

Hello Kei.

That looks correct, as long as there is a > 150 us delay between the end of the previous frame and the start of the next frame(rising edge) and <300 us delay, and that is represented by the pulsewidth of the SYNC_IN rising and falling edges, then that should be a correct diagram.

Sincerely,

Santosh

Hi Santosh,

The requirement that the interval between the end of the previous frame and the start of the next frame (the rising edge of the pulse) should be less than 300 µs is stated as "recommended" rather than "mandatory." Therefore, I believe it is acceptable for this interval to exceed 300 µs. Is my understanding correct?

Regards,
Kei

Hello Kei.

If it is recommended not to go over that time limit, I would not suggest going over that limit as it may result in unintended behavior that was not characterized or not supported by the device firmware.

Sincerely,

Santosh

Hi Santosh,

Thank you for your reply.
I believe that the frame trigger delay (denoted by δ in the figure below) is set by 7th parameter of frameCfg, and frame periodicity (denoted by T in the figure) is set by 5th parameter.
Is this correct?

Also, if T+δ +150us < SYNC_IN Periodicity < T+δ + 300us is required and SYNC_IN pulse periodicity is fixed (e.g., 100ms), then I need to configure the frame time to be between 99.70 ~ 99.85 (with a frame trigger delay of 0).
Is my understanding correct?

Regards,
Kei

Hello Kei.

Kei said:

I believe that the frame trigger delay (denoted by δ in the figure below) is set by 7th parameter of frameCfg, and frame periodicity (denoted by T in the figure) is set by 5th parameter.
Is this correct?

You are correct.

Kei said:

Also, if T+δ +150us < SYNC_IN Periodicity < T+δ + 300us is required and SYNC_IN pulse periodicity is fixed (e.g., 100ms), then I need to configure the frame time to be between 99.70 ~ 99.85 (with a frame trigger delay of 0).
Is my understanding correct?

I believe that is correct, though I don't know if those numbers are inclusive of those boundaries.

Sincerely,

Santosh

Hi Santosh,

Thank you for your reply. I understand the explanation. I have one final question: Why must the interval between the end of the previous frame and the start of the next frame (i.e., the rising edge of the pulse) be less than 300 µs? I understand that a minimum interval (e.g., 150 µs) is specified, but I am unclear why there is also a maximum limit (e.g., 300 µs).

Regards,
Kei

Hello Kei.

Let me look into this and provide an update by the end of the day.

Sincerely,

Santosh

Hi Santosh,

Could you please provide an update on this?

Regards,
Kei

Hello TI team,

Could you please provide an update on this?

Regards,
Kei

Hello Kei.

Apologies for the delay in response as I was out of town last week.  Let me continue to look into this and provide an update by the end of the day tomorrow.

Sincerely,

Santosh

Hello Kei.

The maximum is 300 us to give the internal circuitry time to reset prior to the next frame and the start of chirping.

Sincerely,

Santosh

Hello Santosh,

If the 300 μs is the time required for the internal circuitry to reset before the next frame or chirping, wouldn't it be acceptable for it to exceed 300 μs? Could you please explain in detail why it must not go beyond 300 μs?
I am concerned that if the period of the SYNC_IN pulse is not precise (due to individual differences or temperature variations), it will not be possible to use the same "frameCfg" settings across all devices.

Regards,
Kei