Tool/software:
Dear TI Support Team,
The below is the phrase from Reference Manual
"RBL can load the SBL content only to MSS_L2 area and at the end copies SBL's IVT (interrupt vector table) of
640B size to TCMA_RAM_CR5A before switching to SBL. This ROM-to-RAM (RBL to SBL) switching causes
TCMA_ROM_CR5A eclipse to TCMA_RAM_CR5A i.e. 0x0000_0000 now maps to TCMA_RAM_CR5A memory
area."
I have configured my project to allocate exception vector table at 0x00020000.
But when I run the software on the board, I saw that the R5 core is still using the exception vector table at address of TCMA_ROM_CR5A (0x00000000) which is not desired table.
I have the following questions.
1. Do I miss set up some configuration or registers for mapping exception vector table to 0x00020000?
2. Does the configuration of SOP (Functional and Flashing mode) affect this feature?
Thanks,
Dang