AWR2E44PEVM: How to reduce 1.0V ripple?

The location of the capacitors will play a very important role here to reduce the ripple. 

Can you share your layout?

-E. Shareef

Hi Shareef,

Please see the yellow part. Capacitors are in the red frame.

The positioning of the capacitors seem ok. 

Where are you probing on this measurement?

What is the PMIC you are using? Or is there only the LDO?

How many caps do you have in your circuit for the 1V?

-E. Shareef

Hi Shareef,

    We both test on the PMIC side and SoC side, the phenomenon is the same.

We use LP87745-Q1. You can see the pictures.

The Caps are placed appropriately. 

Allow me to discuss with my team and respond shortly.

E. Shareef

Hi Shareef,

     Do you have any other solutions?

Hello Xin,

We are still discussing this internally and will respond shortly.

E. Shareef

Hi，

    This is the zoom in waveform.

What is the ADC sampling rate used ?

E. Shareef

Hi，

    It is 37500ksps.

This should be fine. I will send you a plot shortly explaining the transient.