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AWR2944: Probability of failure when configuring pmic watchdog from enable to disable

Chris Sun
Prodigy 110 points
Part Number: AWR2944

Tool/software:

The project requires implementing the functionality to enable the PMIC watchdog in the application (app) and disable it in the bootloader (boot).

For OTA, the system needs to transition from the app to the boot for the upgrade process.
Since the PMIC watchdog is enabled in the app, it cannot be directly disabled after transitioning to the boot.
Currently, before transitioning from the app to the boot, I first write to bit 0 (WD_RETURN_LONGWIN) of the PMIC register WD_MODE_REG via mibspi.
Then, I wait for 500 milliseconds and perform a warm reset to jump to the boot.
In the boot, I disable the watchdog by writing 0 to the PMIC register WD_ENABLE_REG.


My issue is that there is a probability of failure in the PMIC watchdog configuration during this process,
which prevents the watchdog from being properly disabled in the boot.

Could you please help identify the root cause of this problem and suggest how it should be resolved?

  • 0
    Prodigy 110 points

    The parameters for win1, win2,  the long window timeout, WD_FAIL_TH, WD_RST_TH are all based on the OTP parameters stored in the NVM.

  • 0 in reply to Chris Sun
    TI__Genius 10920 points

    Hi Chris,

    The expert is out of office currently. Please expect a delay in response.

    Regards,

    Shruti

  • 0 in reply to Chris Sun
    TI__Mastermind 35125 points

    Hello Chris,

    Why can the watchdog not be disabled in the application before performing the warm reset?

    Regards,
    Saswat Kumar

  • 0 in reply to Saswat Kumar
    Prodigy 110 points

    Hello Saswat,

    The following are several reasons:

    1. According to the technical manual, my understanding is that once the PMIC watchdog has been enabled, it cannot be directly disabled.
    Instead, it must first be configured to LONG WINDOW mode.
    Afterward, it is necessary to wait for a Watchdog Sequence (the original text states "after the current Watchdog Sequence completes").
    I interpret this as needing to wait for the combined duration of win1 and win2. Therefore, I added a 500ms delay to account for this.

    If my understanding here is incorrect, please kindly point out the mistake.

    2. Since the method of configuring registers to perform a warm reset was used to restart the software, by calling `SOC_generateSwWarmReset()`,
    is there a possibility that the reset could fail, causing the system to hang?
    In such a case, the system might recover via the watchdog.
    Therefore, the watchdog was not disabled before performing the warm reset.

    3. If we need to disable the watchdog before performing a warm reset, how should this be done?
    Should we also configure the LONG WINDOW mode before the warm reset, wait for 500ms, and then configure the register to disable the watchdog?

    Regards,
    Chris

  • 0 in reply to Chris Sun
    TI__Mastermind 35125 points

    Hello Chris,

    Looks like what you have mentioned is from the PMIC TRM.
    Let me try to loop in a PMIC expert here to help answer your queries.

    Regards,
    Saswat Kumar