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AWRL6844: L3 memory retention in LPM mode

Part Number: AWRL6844
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Hello team,

.

My customer set as below but still L3 memory doesn't look retained. Can we provide guidance how to retain L3 memory? What are they missing?

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Sysconfig

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in DPC_Execute

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Regards,

Victor Park

  • Hi Victor,

    Thank you for reaching out. I would like to ask some questions to better understand what is going on. 

    1. Which demo are they running?
    2. Can you elaborate on the behavior you seeing when you mention that L3 is not being retained? Is there memory stored in L3 which becomes corrupted after exiting deep sleep?
    3. Is the demo not functioning in low power mode only? Does it work in non low power mode?

    Best,

    Vignesh K.

  • Hello Vig,

    .

    They've been testing with their own application but today they tested it with SDK(v 6.0.4.1) demo and it has same issue as well. They used 0x88037220(MmwMssMCB.dpcAoAObjSideInfo) address as L3 memory and application increases value in each Frame. In DPC_Execute(), there is Update_counter_at_address() and it increases value every Frame. And then, application sends current_value through CAN in Demo_transmitProcessedOutputTask(). Now, customer checked current_value in CanOe.

    .

    When low power mode is off, system retains memory.

    When low power mode is on, seems L3 memory is initialized as zero even with sysconfig setting below.

    .

    Regards,

    Victor Park

  • Hi Victor, 

    Is there a reason for using that exact address?

    Alternatively, you can try using the attribute keyword:

    __attribute__((section(".bss.l3"))) uint8_t current_value = 0;
    Best,
    Vignesh K.
  • Hello Vignesh,

    .

    Customer has tested with your guidance but result is same. Please refer below code.

    .

    /*! L3 RAM buffer for object detection DPC */

    uint8_t                         gMmwL3[L3_MEM_SIZE]  __attribute((section(".bss.l3")));

    #define TARGET_ADDRESS ((volatile uint8_t *)&gMmwL3[L3_MEM_SIZE - 1])  

    .

    With this code, it works well when LPM is disabled. It doesn't work when LPM is enabled.

    .

    .

    Regards,

    Victor Park

  • Hi Victor, 

    Could you share the linked command?

    I will get back to you by the end of this week after looking further into this. 

    Best,

    Vignesh K.

  • Hello Vignesh,

    .

    Here is linker command file.

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/1023/0602.linker.cmd

    .

    Regards,

    Victor Park

  • Hi Victor,

    Thank you for providing this. While I continue to debug this issue on my end, I am wondering what the customer is trying to achieve here. It looks like they are interested in working with CAN. Are you aware of our CAN Integration Guide

    Best,

    Vignesh K.

  • Hello Vignesh,

    .

    I couldn't fully understand your point. For this issue, they use CAN communication to check the L3 memory data. They confirmed there is no issue when LPM mode is disabled. Meaning, CAN communication has no problem when they test it. If you could explain more detail about your guidance point, I could deliver that to customer.

    .

    Regards,

    Victor Park

  • Hello Victor,

    I apologize for the confusion. I understood the issue incorrectly. 

    Could you do the following:

    1. Load your program in CCS
    2. Within the Power_sleep function under <MMWAVE_LSDK6_INSTALL_DIR>/sources/drivers/power/v0/power_xwrLx4xx.c, set a breakpoint on line 687 and run your program
    3. Upon hitting the breakpoint which should occur whenever the device attempts to enter LPDS, check the following addresses using the Memory Viewer in CCS:
      1. 0x5A04041C
        0x5A040014
        0x5A040430
        0x5A040434
        0x5A040438
        0x5A040670
        0x5A040674
        0x5A040678
        0x5A04067C
    4. Check the above addresses after exiting LPDS as well.

    The likely reason why your L3 is not being retained is caused by a value not being configured properly either before or after LPDS and reading these memory addresses will allow us to confirm this.

    Best,

    Vignesh K.

  • Hello Vignesh,

    Thanks for sharing debugging points! 

    Actually customer is using SDK v6.0.4.1. Anyway, they set breakpoint at same function(PRCMSetPSCONDFTRTAOverride) and checked the addresses before the line is executed and after the line executed. The values are same. When they set breakpoint at function(PRCMSetSRAMRetention) all the address values are also same.

    .

    0x5A04041C : 00000003

    0x5A040014 : 000F000F

    0x5A040430 : 00070007

    0x5A040434 : 00030003

    0x5A040438 : 00010001

    0x5A040670 : 00070007

    0x5A040674 : 00030003

    0x5A040678 : 000F0003

    0x5A04067C : 00070007

    .

    I think the breakpoint location you mentioned is 'before getting in LPDS mode'. If you want to see the values after 'LPDS mode', please guide me where exactly customer need to set breakpoint and check values.

    Regards,

    Victor Park

  • Hey Victor, 

    Thank you for reading out those values. We should look at them after exiting LPDS as well. The easiest way to do this is to set another break point in the Power_sleep function at the following line of code:

    Power_module.state = Power_EXITING_DEEPSLEEP; //line 531
    Best,
    Vignesh K.
  • Hello Vignesh,

    .

    They've tested that but the value looks same. What would be next debugging step? Is it something we could reproduce at your side? As customer has to show low power mode demo at the end of the month, they need quick help. If you think it is good idea, let me arrange meeting for co-debugging in real-time early next week.

    0x5A04041C : 00000003

    0x5A040014 : 000F000F

    0x5A040430 : 00070007

    0x5A040434 : 00030003

    0x5A040438 : 00010001

    0x5A040670 : 00070007

    0x5A040674 : 00030003

    0x5A040678 : 000F0003

    0x5A04067C : 00070007

    .

    Regards,

    Victor Park

  • Hi Victor,

    I have root caused the issue to the SOC_memoryInit function from the power_LPDSresumehook function. In order to retain memory in L3 between LPDS, you must remove SOC_MEMINIT_DSS_L3_NATIVE_RAM0_INIT|SOC_MEMINIT_DSS_L3_NATIVE_RAM1_INIT from memory init.

    So the following modification:  

        //line 227 in power_management.c in the power_LPDSresumehook function
        SOC_memoryInit(SOC_MEMINIT_APPSS_SHARED_TCMA_BANK0_INIT|SOC_MEMINIT_APPSS_SHARED_TCMA_BANK1_INIT|SOC_MEMINIT_APPSS_SHARED_TCMB_INIT|SOC_MEMINIT_FECSS_SHARED_RAM_INIT|SOC_MEMINIT_APPSS_TPCC_INIT|SOC_MEMINIT_DSS_TPCC_INIT); 
     
    In summary, L3 was being retained but the SOC_memoryInit function was clearing it in the initialization. In order to keep the value, we must not re-initialize L3 which is why we remove SOC_MEMINIT_DSS_L3_NATIVE_RAM0_INIT|SOC_MEMINIT_DSS_L3_NATIVE_RAM1_INIT from that function.
    Best,
    Vignesh K.
  • Hello Vignesh,

    Thank you so much for the solution! Now the memory retains! By the way, can I ask why our code reinitialize the memory regardless of Syscfg memory retention setting? Is there any intention for the code?

    .

    Regards,

    Victor Park

  • Hey Victor,

    Good question, I believe that L3 is always reinitialized because we generally don't keep HWA memory between frames. Additionally, some memory must be re-initialized for the clocks to be un-gated. 

    Best,

    Vignesh K.