AWR2544LOPEVM: CSI2 Packetization Configurations

Hello QHLam,

What is the driver you are using for this?

Regards,
Saswat Kumar

Hello Saswat, 

I am using cbuff driver as the base driver. It is inside mcu_plus_sdk_awr2544_10_00_00_07/source/drivers/cbuff/v0 folder. I added cbuff_csi2.c module to enable CSI2 interface instead of LVDS.

cbuff_csi2.c module has the following functions: 

int32_t CBUFF_initCSI2(CBUFF_Object* ptrDriverMCB, int32_t* errCode);
int32_t CBUFF_deinitCSI2(CBUFF_Object* ptrDriverMCB, int32_t* errCode);
int32_t CBUFF_openCSI2(CBUFF_Session* ptrSession, int32_t* errCode);
int32_t CBUFF_closeCSI2(CBUFF_Session* ptrSession, int32_t* errCode);

Then select CSI2 high-speed interface in CONFIG_REG_0 in CBUFF_initCSI2() function: 

        /* Select the CSI2 high speed interface: 0 : Send data over CSI-2, 1 : Send data over LVDS */
        ptrDriverMCB->ptrCBUFFReg->CONFIG_REG_0 = CSL_FINSR (ptrDriverMCB->ptrCBUFFReg->CONFIG_REG_0, 0U, 0U, 0U);

And I also set the values of packetization configuration registers mentioned in above post inside CBUFF_initCSI2() function as well. I just don't know which value should be used in case of CSI2 interface because I couldn't find their values inside awr2544 technical reference manual. 

        /* Is the CRC Enabled on the LVDS? */
        if (ptrDriverMCB->initCfg.lvdsCfg.crcEnable == 0U)
        {
            /* NO: CRC is not enabled on the LVDS; setup the HSVAL and HEVAL
            * as per the specification */
            ptrDriverMCB->ptrCBUFFReg->CFG_CMD_HSVAL = 0xAAAAAAAAU;
            ptrDriverMCB->ptrCBUFFReg->CFG_CMD_HEVAL = 0xAAAAAAAAU;
        }
        else
        {
            /* YES: CRC is enabled on the LVDS; setup the HSVAL and HEVAL
            * as per the specification */
            ptrDriverMCB->ptrCBUFFReg->CFG_CMD_HSVAL = 0x55555555U;
            ptrDriverMCB->ptrCBUFFReg->CFG_CMD_HEVAL = 0x33333333U;
        }

        /* Setup the registers as per the specification: */
        ptrDriverMCB->ptrCBUFFReg->CFG_SPHDR_ADDRESS = 0x55555555U;
        ptrDriverMCB->ptrCBUFFReg->CFG_LPHDR_ADDRESS = 0x55555555U;
        ptrDriverMCB->ptrCBUFFReg->CFG_CMD_VSVAL     = 0xAAAAAAAAU;
        ptrDriverMCB->ptrCBUFFReg->CFG_CMD_VEVAL     = 0xAAAAAAAAU;

Thanks and appreciate your support!

Best, 

QHLam

Hello Saswat, 

Finally, I find a reference csi driver from mmwave_sdk (version 3.6.2.0, for xWR14xx) and port it into mcu_plus_sdk for awr2544. However, surprisingly I couldn't see CSI Protocol Engine base address and CSI PHY base address defined in cslr_soc_baseaddress.h header file of mcu_plus_sdk. And awr2544 TRM didn't mention about CSI protocol engine/CSI Phy base address in memory map table neither. This makes me very confused. I believe awr2544 does support CSI2 TX.

A few questions: 

1. Is CSI2 engine of xWR14xx compatible with the one on awr2544? Are their registers maps similar? If yes, would you please share me CSI Protocol Engine base address and CSI PHY base address. I have csi driver and unit test ported successfully into mcu_plus_sdk, but failed to run because of missing the base address of CSI block. 

2. On the other hand, if they are not compatible, and not able to expose CSI2 related technical document of awr2544 SoC at the moment. Would you please share the development and release plan to support this feature? 

Thanks and appreciate your support!

QHLam

Hello QHLam,

As the team is on holiday.
Let me cross check and get back to you by wednesday.

Regards,
Saswat Kumar

Hello Saswat, 

That's a great news. I should have to wait for the SDK update with csi2 tx reference application by early next month.

Thank you so much for your support.

Best, 

QHLam

Hello Saswat, 

Have you got any update from the team for the SDK update release? 

Thanks, 

Quoc

Hello QHlam,

By coming Monday it should be up. There might be 1/2 days delay for some of the approvals.

Regards,
Saswat Kumar

Hello Saswat, 

That's good to know. Looking forward to it. 

Best, 

Quoc