• State Resolved
  • Locked Locked
  • Replies 9 replies
  • Answers 3 answers
  • Subscribers 30 subscribers
  • Views 343 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AWR2243: About LO line link budget

Manwoo Kim
Prodigy 170 points
Part Number: AWR2243

Tool/software:

Hi, All!

I have question about LO link budget, when I design cascading system using AWR2243.

AWR2243 LO output power is typical 7dBm, and input range is -6~7dBm.

When I used two AWR2243, what‘s the best LO input power??

(I want to know what’s the best my target PCB loss.)

Thanks,

  • 0
    Prodigy 170 points

    Hi, All

    Please check this question!

    Thanks,

  • 0
    TI__Expert 5461 points

    Hi Manwoo,

    Sorry for the delay due to the long weekend. Please refer to the following application note, section 4 on the link budget and kindly let me know if any further clarification is needed. 

    AWR2243 Cascade (Rev. B)

    Regards,

    Aydin

  • 0 in reply to Aydin Kiasat
    Prodigy 170 points

    Hi, Aydin!

    Thanks for your reply!

    I already read the document, but I can't find what's the best LO input power.

    If LO input power is within recommend LO input power range, LO input power is not important?

    (-6dBm and 7dBm is same performance?)

    Thanks,

  • 0 in reply to Manwoo Kim
    TI__Expert 5461 points

    Hi Manwoo,

    Yes, any LO input power between -6 and +7 dBm is within spec, but for best performance, you want the LO input at around +3 to +6 dBm. That means targeting around 1–4 dB of total LO path loss from the master’s LO_OUT to the slave’s LO_IN to give optimal phase noise and PLL performance. Please confirm the loss with the board material you are using through simulation. 

    Regards,

    Aydin 

  • 0 in reply to Aydin Kiasat
    Prodigy 170 points

    Hi, Aydin!

    Thanks for your kind answer.

    MMIC has best LO input power for optimal phase noise and PLL generally?

    Is it critical value? (how to different (3~6dBm) and (-6~3dBm))

    Thanks,

  • 0 in reply to Manwoo Kim
    TI__Expert 5461 points

    Hi Manwoo,

    Yes, even though the AWR2243’s LO input spec allows wide range of –6 dBm to +7 dBm, we generally recommend targeting around +3 to +6 dBm at the LO input for best performance. This provides optimal phase noise and PLL margin, especially considering any PCB trace loss, material variation, or temperature related drift over time. So, the recommendation to stay near +3 to +6 dBm just ensures consistent LO drive and robustness. 

    Regards,

    Aydin

  • 0 in reply to Aydin Kiasat
    Prodigy 170 points

    Hi, Aydin!

    Thanks for your reply.

    Is this recommended from a robustness perspective? Then, under the same conditions, what's the differnece between + 3dBm and -3dBm? Is there a performance difference?

    Thanks,

  • 0 in reply to Manwoo Kim
    TI__Expert 5461 points

    Hi Manwoo,  

    To clarify, when I mentioned “robustness,” I was referring to having sufficient headroom. At the end of the day, it really comes down to how much LO path loss you have between devices. While both –3 dBm and +3 dBm are within spec, in practice, you always want to design with margin, not right at the lower edge. This ensures that any additional loss from PCB routing, or long term variation doesn’t push the signal below the minimum required level. 

    However, are you designing a 2 chip or 4 chip AWR2243? If 2chip, you do not need a Wilkinson divider as you can directly short FMCW_CLK_OUT to FMCW_SYNCIN2. However, in 2188, 2 chip cascade, you need to have a Wilkinson divider. 

    Regards,

    Aydin 

  • 0 in reply to Aydin Kiasat
    Prodigy 170 points

    Hi, Aydin!

    Thanks for your reply.

    I understood it's for suffcient headroom!

    Thanks,