AWR1843AOP: QSPI CLK INQUIRY

MINKYU CHOI

Part Number: AWR1843AOP

Tool/software:

When using the PIN (H2) as a QSPI CLK function, the address setting is specified in the data sheet as 'PULL DOWN'.

If there is no pull-up circuit in the external QSPI communication interface circuit, should I change the internal (AOP) address setting to the 'PULL UP' setting?

Or will the 'PULL DOWN' setting allow communication without external pull-up?

3 months ago

0 Kundan Somala 3 months ago

TI__Expert 3670 points

Minkyu Choi, Thanks for reaching out to us over E2E.

External Pull-up is not required for QSPI_CLK signal. The QSPI communication works fine without any external pull-up on the CLK line.

Thanks,
Kundan

0 MINKYU CHOI 3 months ago in reply to Kundan Somala

Prodigy 140 points

Hi, Kundan.

If there is no pull-up on the outside, and there is no pull-up on the inside, how can we judge high-low? Clk counts as high/low edge to create and judge clk. If it works with qspi's clk function, will the pull-up/pull-down setting become meaningless? Does it only work with a specific function of qspi's clk?

regards,

choi

0 MINKYU CHOI 3 months ago in reply to Kundan Somala

Prodigy 140 points

Does it only work as a function of qspi clk? Or does it work as a push-pull driver?

0 Kundan Somala 2 months ago in reply to MINKYU CHOI

TI__Expert 3670 points

During the flashing mode/loading the appimage from flash, it acts as QSPI CLK. You can configure this Pin to a different functionality in your application as desired.

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AWR1843AOP: QSPI CLK INQUIRY