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AWR1843BOOST: DPU memory allocation.

yifan zhu
Intellectual 255 points
Part Number: AWR1843BOOST

Tool/software:

Hi:

I'm now developing based on OOB demo of 1843boost. Currently I've modify the code so the whole DPC chain is running purely on DSP. I would like to know how the whole DPC memory is allocated. I checked the manual and it seems like the memory 0x5100_0000~0x51FF_FFFF is allocated as L3RAM for DDS as a shared memory. Is this memory  address fixed somehow or it is configured during the DPC_ObjDetDSP_preStartConfig? I went through the code and I'm sure there are memory allocation operation there but the allocated address start from 0x0080_xxxx etc. How does this memory allocation operation related to the 0x5100_0000?

Regards

  • 0
    TI__Mastermind 19980 points

    Hi Yifan,

    Below is the screenshot from Table 3-3. DSP C674x Memory Map of AWR18xx/16xx/14xx Technical Reference Manual (Rev. E) where you can check the address of DSS_L3.

    yifan zhu said:
    I checked the manual and it seems like the memory 0x5100_0000~0x51FF_FFFF is allocated as L3RAM for DDS as a shared memory

    Address that you mentioned is the address of DSS_L3 when viewed from MSS (not DSS). 

    yifan zhu said:
    Is this memory  address fixed somehow or it is configured during the DPC_ObjDetDSP_preStartConfig?

    We use DSS_L3 to store the processing chain results. You can store the results on other memories but since DSS_L3 is large enoungh to store radarcube, detection matrix, we use DSS_L3 instead of other memory regions. 

    yifan zhu said:
    I went through the code and I'm sure there are memory allocation operation there but the allocated address start from 0x0080_xxxx etc

    This is the start address of DSP L2 RAM which is the local RAM buffer defined in demo. We use DSS_L3 as well as DSP L2 in the application.

    You can refer to C:/ti/mmwave_sdk_03_06_02_00-LTS/packages/ti/datapath/dpc/objectdetection/objdethwa/docs/doxygen/html/index.html document to get detailed understanding of the current memory layout.

    Regards,

    Samhitha 

  • 0 in reply to Samhitha Bobba
    Intellectual 255 points

    I see, I understand the radar cude starts from 0x5100_0000, I just fustrated since I checked the radar cude memory allocation in code and seems like it is not initialized to 0x5100_0000, can you help me locate the code that allocate 0x5100_0000 to radar cude? Also, does DSP-based DPC uses same memory allocation? 

    Regards

  • +1 in reply to yifan zhu
    TI__Mastermind 19980 points

    Yifan,

    As mentioned in my previous reply, DSS_L3 starts from 0x20000000 when viewed from DSP. I hope you are looking for address of DSS_L3 when viewed from DSP, it would be 0x20000000.

    In dss_main.c file. you can see that through DATA_SECTION pragma, we allocate space for gMmwL3 variable in ".l3ram" which is loaded onto L3SRAM (check mmw_dss_linker.cmd). You can find the memory allocations of L3SRAM section in "C:\ti\mmwave_sdk_03_06_02_00-LTS\packages\ti\platform\xwr18xx\c674x_linker.cmd". Space for gDPC_ObjDetL2Heap is allocated in ".dpc_l2Heap" which is loaded onto L2SRAM_UMAP0 (DSP_L2).

    Core local RAM which is DSP_L2 RAM where intermediate results are stored, starts from 0x00800000. I suggest you to check the linker files to understand the start address of different memory locations used in the application.

    Regards,

    Samhitha