• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 30 subscribers
  • Views 53 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AWR1843BOOST: DPU data memory location and allocation

yifan zhu
Intellectual 255 points
Part Number: AWR1843BOOST

Tool/software:

Hi:

I got some issue when idenfitying the specific memory location of DPUs. According to the xWR Radar Tech Ref Manual, I can see L3 RAM starts from 0x5100_0000 and L3 RAM is used for the DPIF_RadarCube (output of rangeProc DPU). However, I would also want to know where are the DPIF_DETMATRIX, DPIF_CFARDetList_t and DPIF_PointCloudCartesian located. Another problem is when I go through the demo code, I can see the memory allocated for radar cube is 0x2000_0000, which is not 0x5100_0000 so I guess there must have some mapping mechanism, is there any detailed document that I can use to check the memory mapping?

Regards

  • 0
    TI__Guru*** 147854 points

    Hi,

    Regarding memory maps, please remember that the AWR1843BOOST has two cores, ARM and DSP. Each core has a memory map. Please check the memory maps in the TRM.

    It seems that your questions are based on the mmWave SDK 3.6 OOB demo.

    The memory is allocated as arrays

    Please see in dss_main.c:

    /*! L3 RAM buffer for object detection DPC */
    uint8_t gMmwL3[SOC_L3RAM_SIZE];
    #ifndef SOC_XWR68XX
    /* EDMA 4K silicon bug related : Align heap to 4K address boundary so that
     * non heap related changes (such as program code) does not alter the 4K related
     * behavior */
    #pragma DATA_ALIGN(gMmwL3, 4096U);
    #endif
    #pragma DATA_SECTION(gMmwL3, ".l3ram");

     /*! L2 RAM buffer for object detection DPC */
    #define MMWDEMO_OBJDET_L2RAM_SIZE (49U * 1024U)
    uint8_t gDPC_ObjDetL2Heap[MMWDEMO_OBJDET_L2RAM_SIZE];
    #ifndef SOC_XWR68XX
    /* EDMA 4K silicon bug related : Align heap to 4K address boundary so that
     * non heap related changes (such as program code) does not alter the 4K related
     * behavior */
    #pragma DATA_ALIGN(gDPC_ObjDetL2Heap, 4096U);
    #endif
    #pragma DATA_SECTION(gDPC_ObjDetL2Heap, ".dpc_l2Heap");

     /*! HSRAM for processing results */
    #pragma DATA_SECTION(gHSRAM, ".demoSharedMem");
    #pragma DATA_ALIGN(gHSRAM, 4);
    This information is passed to the ObjectDetection DPC

        objDetInitParams.L3ramCfg.addr = (void *)&gMmwL3[0];
        objDetInitParams.L3ramCfg.size = sizeof(gMmwL3);
        objDetInitParams.CoreL2RamCfg.addr = &gDPC_ObjDetL2Heap[0];
        objDetInitParams.CoreL2RamCfg.size = sizeof(gDPC_ObjDetL2Heap);
        objDetInitParams.CoreL1RamCfg.addr = &gDPC_ObjDetL1Heap[0];
        objDetInitParams.CoreL1RamCfg.size = sizeof(gDPC_ObjDetL1Heap);
    The ObjectDetection module uses APIs to manage memory pools see for example the APIs with MemPool
    Pools are defined and memory is allocated from these pools through MrmPoolAlloc() APIs
    C:\ti\mmwave_sdk_03_06_02_00-LTS\packages\ti\datapath\dpc\objectdetection\objdetdsp\src\objectdetection.c
    This demo was developed a long time ago and the team that developed the code is no longer available for support.
    The source code is basically all the information we have about the code
    thank you
    Cesar