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AWR2E44PEVM: QSPI issue

Chen Yu
Prodigy 20 points
Part Number: AWR2E44PEVM

Tool/software:

Hello,

We are using AWR2E44P, and W25Q32JV as the external flash. We are using the memmap mode to read the data during initialization.

I have doubt that we don't set the read length in any register, only set the start address and 0x6B command, how we can realize the read action?

Another question is related to 0x6B command, the flash chip shows the sequence should be cmd+addr+dummy+data0+data1+data2+....., however from the testing log, it shows cmd+addr+dummy+data0 repeat cmd+addr+dummy+data1......

Whether I can use the 0xEB command to realize cmd+addr+dummy+data0,1,2,3....?

  • +1
    TI__Genius 11220 points

    Hi Chen, 

    Apologies for the delay. Have you checked the qspi flash transfer example available in the SDK? The example demonstrates the transfer of a data block from the flash.

    Sharing the path for the same:

    ti\mmwave_mcuplus_sdk_04_07_00_01\mcu_plus_sdk_awr2x44p_10_00_00_07\examples\drivers\qspi\qspi_flash_transfer

    Let me know if this works or you need any further details here.

    Regards,

    Shruti

  • +1 in reply to shruti gupta
    Prodigy 20 points

    Hello，

    I checked the sdk, still have some doubts:

    1. in the code the address should be 4 bytes alignment. for the rest still memcpy are used, why?

    2. I would like to use the DBS for 128 bytes, in this case, do I need to have 128 bytes alignment for the src and dest, also for the block length?

  • +1 in reply to Chen Yu
    Prodigy 20 points

    I see the sdk and integrated the Cdd_dma module in my project, however, it seems doesn't work for read. The logic analyzer shows no signal at all!

    My configuration is as below. 

    The generated code in Mcal is as below, as I didn't configure the ISR for the EDMA, polling read the status and software is structed by ready the status!

  • +1 in reply to shruti gupta
    Prodigy 20 points

    In the forum, I see someone said the SOC can only support command+addr+dummy+1byte(or 4 byte)? Is it true? Even use QSPI+DMA, can we realize 1comand+addr+dummy+byte1+byte2+byte.....(continuous byte)

  • +1 in reply to Chen Yu
    Prodigy 20 points

    I have use the sdk for QSPI+EDMA and it works to obtain 16 bytes continuously read. however, DBS register seems doesn't work. I configure the MSS_CTRL: TPTC_DBS_CONFIG to 3, the byte number is always 64 bytes but not 128 bytes, if configure as 2, the byte number is 64, if configure as 1, the byte number is 32! what may cause the byte number limit to 64?

  • 0 in reply to shruti gupta
    Prodigy 20 points

    Hello, 

    I have successfully integrated QSPI+EDMA in APP software, however, I migrate to Boot, it doesn't work.

    When called Cdd_Dma_EnableTransferRegion function, ERRDET = 0x00010009, bus error. How to analyze the cause? I don't know what it means for that value and what should I step future?

    Additional information, with logic analyzer the wave is OK, the source address and value are all correct, however, the destination address values are not updated!