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AWR2544LOPEVM: AWR2544LOPEVM with GMSL2

QHLam
Prodigy 210 points
Part Number: AWR2544LOPEVM
Other Parts Discussed in Thread: AWR2544

Tool/software:

Hi, 

I'm testing with awr2544 CSI-TX OOB demo with GMSL2 MAX96717 serializer chipset. I have followed ECO instruction to make all CSI2 lanes correctly map between awr2544 and gmsl dev kit. 

By reading max96717 csi phy counter registers, I confirmed that serializer chip has received csi clock and data from radar chip but it failed to detect a pixel. I have both radar and serializer chip data-type set to RAW8 (0x2A). 

Would you please confirm with awr2544 csi-tx full compliance with mipi video pixel mode? 

Thanks, 

Lam

  • 0
    TI__Mastermind 35445 points

    Hello Lam,

    We do not support the mipi video pixel mode.

    Regards,
    Saswat Kumar

  • 0 in reply to Saswat Kumar
    Prodigy 210 points

    HI Saswat, 

    So sorry, I mean whether or not awr2544 CSI2-TX supports CSI-2 transmission format similar to a video pixel frame e.g. Frame Start/End short package, Line Start/End short package..etc.

    I think CSI stream sending out from awr2544 is pixel mode compatible, however I have an issue that the CSI receiver is unable to decode a valid CSi-2 clock from awr2544 CSI-TX. 

    Would you please let me know where in CSI-TX driver to adjust PHY timing and DDR clock timing? 

    Thanks and appreciate your help!

    Quoc Lam

  • +1 in reply to QHLam
    TI__Mastermind 35445 points

    Hello Lam,

    You can refer the registers:

    and it happens in the code:


    The clk is the hsiClock which we set in the application:

    This selection of clock value is based on what the Per_PLL is configured to for example:
    if its 1200 Mhz, then the Data rate is 600 Mbps
    Is its 900 Mhz, Data rate is 450 Mbps.
    So its clock/2 to give you the data rate value which needs to be configured.

    Regards,
    Saswat Kumar